[PATCH] D131959: [AMDGPU] Fix SDST operand of V_DIV_SCALE to always be VCC

[Pierre van Houtryve via Phabricator via llvm-commits]

Pierre-vh added a comment.

In D131959#3763862 <https://reviews.llvm.org/D131959#3763862>, @foad wrote:

>> However, it incorrectly assigns VReg_1 for the register class of the VCC copy it emits in InstrEmitter.
>
> Why is VReg_1 wrong? In some places that is the class we use for an SGPR (or SGPR pair) that represents an independent 1-bit value per lane. Why doesn't that work here?

It indeed seems to be used to represent a i1 when the value is divergent. Though I'm not sure why, but if I don't correct the regclass to an SReg, the LowerI1Copies pass cannot handle it.

Perhaps the issue lies in LowerI1Copies? I don't understand that pass well enough to know if the assertion is legitimate, or a sign of an unhandled case.
It seems like, to me, it shouldn't be lowering the VCC copy to a specific instruction but rather only lower it when it's actually needed (when the value needs to be preserved).

  [build] llc: llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp:713: bool (anonymous namespace)::SILowerI1Copies::lowerCopiesToI1(): Assertion `TII->getRegisterInfo().getRegSizeInBits(SrcReg, *MRI) == 32' failed.
  
  [build]   LLVM :: CodeGen/AMDGPU/dpp64_combine.ll
  [build]   LLVM :: CodeGen/AMDGPU/fcanonicalize-elimination.ll
  [build]   LLVM :: CodeGen/AMDGPU/fdiv-nofpexcept.ll
  [build]   LLVM :: CodeGen/AMDGPU/fdiv.f16.ll
  [build]   LLVM :: CodeGen/AMDGPU/llvm.powi.ll
  [build]   LLVM :: CodeGen/AMDGPU/rsq.ll
  [build]   LLVM :: CodeGen/AMDGPU/sgpr-copy.ll
  [build]   LLVM :: CodeGen/AMDGPU/si-sgpr-spill.ll
  [build]   LLVM :: CodeGen/AMDGPU/wave32.ll
  `


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131959/new/

https://reviews.llvm.org/D131959