[PATCH] D131959: [AMDGPU] Fix SDST operand of V_DIV_SCALE to always be VCC

[Jay Foad via Phabricator via llvm-commits]

foad added a comment.

> However, it incorrectly assigns VReg_1 for the register class of the VCC copy it emits in InstrEmitter.

Why is VReg_1 wrong? In some places that is the class we use for an SGPR (or SGPR pair) that represents an independent 1-bit value per lane. Why doesn't that work here?


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  https://reviews.llvm.org/D131959/new/

https://reviews.llvm.org/D131959