[PATCH] D133063: [docs] Add a RISC-V Usage page

Thu Sep 1 05:57:07 PDT 2022

asb added a comment.

Thanks for kicking this off - it's a great idea! I left a few notes inline. One thing I'm wondering about is what level of information it might be useful to give beyond just "supported". It might for instance be useful to indicate whether support is just at the MC layer or MC layer + codegen. If we were to do so, would just having a "codegen" category that encompasses automatic ISel as well as intrinsics where relevant be sufficient (I think so?).

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Comment at: llvm/docs/RISCVUsage.rst:18
+
+The specification defines three base instruction sets: RV32I, RV64I, and RV128I.
+Currently, LLVM supports RV32I, and RV64I, but not RV128I.
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I think RV32E is typically described as a base instruction set too (albeit one that is actually a subset of RV32I).

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Comment at: llvm/docs/RISCVUsage.rst:53
+     ``V``          Supported
+     ``Zicsr``      Supported
+     ``Zifencei``   Supported
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jrtc27 wrote:
> .. ish, the CSRs are there but we're still at I2P0 so Zicsr doesn't really exist
Plus Zicbop, Zicboz, Zicbom

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Comment at: llvm/docs/RISCVUsage.rst:58
+     ``Zbc``        Supported
+     ``Zbs``        Supported
+     ``Zve32x``     Unsupported
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Also Zbkb, Zbkc, Zbkx. MC layer support for Zfinx/Zdinx too

Plus various Zk* extensions.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D133063/new/

https://reviews.llvm.org/D133063