[PATCH] D133063: [docs] Add a RISC-V Usage page

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added a comment.

Thanks for doing this!



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Comment at: llvm/docs/RISCVUsage.rst:2
+=============================
+User Guide for RISCV-V Target
+=============================
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`RISC-V`


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Comment at: llvm/docs/RISCVUsage.rst:72
+
+Zve32x, Zve32f, Zvl32b
+  LLVM currently assumes a minimum VLEN (vector register width) of 64 bytes.
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Maybe have these back-ticked for consistency?


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  https://reviews.llvm.org/D133063/new/

https://reviews.llvm.org/D133063