[PATCH] D133067: [AMDGPU] W/a hazard if 64 bit shift amount is a highest allocated VGPR

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

In D133067#3763494 <https://reviews.llvm.org/D133067#3763494>, @foad wrote:

>> Also we could still constrain src0 of these to a decimated RC in the finalizeLowering and keep this w/a just in case further optimizations would replace the operand.
>
> If you use a different RC for src0 then surely you don't need the workaround? The rest of the compiler should respect the RC, and should not "replace the operand" with a physreg that is not in the right RC.

That is if I define a whole new set of shifts for this target. This would create a whole new set of problems. If I just constrain existing vgpr32 operand to a decimated RC it will eventually be replaced by some subsequent passes.


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