[PATCH] D132196: [PowerPC] Add combine logic to use MADDLD/MADDHD/MADDHDU in multiply-add patterns

[Ting Wang via Phabricator via llvm-commits]

tingwang updated this revision to Diff 457142.
tingwang added a comment.

(1) Validate pattern by using NumSignBits and SignBitIsZero
(2) Add a test case to show the pattern


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D132196/new/

https://reviews.llvm.org/D132196

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.h
  llvm/test/CodeGen/PowerPC/add-sub-int128-madd.ll
  llvm/test/CodeGen/PowerPC/mulld.ll

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