[PATCH] D132196: [PowerPC] Add combine logic to use MADDLD/MADDHD/MADDHDU in multiply-add patterns

[Ting Wang via Phabricator via llvm-commits]

tingwang added a comment.

The third version has issue that it missed some opportunities that should have been picked up by the second version. For example:

  %conv = sext i64 %a to i128
  %conv1 = sext i64 %b to i128
  %or = or i128 %conv, %conv1
  %mul = mul nsw i128 %conv1, %or
  %conv2 = sext i64 %c to i128
  %add = add nsw i128 %mul, %conv2

It is not obvious to me that `%or = or i128 %conv, %conv1` in the context can be represented by `sext i64 (or i64 %a, %b) to i128`. I'm not aware of any API that can help deduce how many bits are the same as signed bit, so that we can apply truncate here. KnownBits calculates ones and zeros, can work for unsigned case, however cannot help signed case.

After type legalized, then above IRs can be identified. Shall we give v2 a second chance to review?


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https://reviews.llvm.org/D132196