[PATCH] D122918: [RISCV][CodeGen] Support Zfinx, Zdinx, Zhinx, Zhinxmin codegen

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoD.td:105
+let Predicates = [HasStdExtZdinx, IsRV32], DecoderNamespace="RV32Zdinx" in {
+def FLD_IN32X : FPLoad_r<0b011, "ld", FPR64IN32X, WriteFLD64>;
+
----------------
craig.topper wrote:
> Is this something that should have been in the MC layer patch?
No. These don't exist. From the spec:

```
Load-pair and store-pair instructions are not provided, so transferring
double-precision operands in RV32Zdinx from or to memory requires
two loads or stores.
```


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122918/new/

https://reviews.llvm.org/D122918