[PATCH] D133025: [LLVM][AArch64] Replace aarch64.sve.ldN by aarch64.sve.ldN.sret

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/sve-intrinsics-ldN-reg+imm-addr-mode.ll:1
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=aarch64--linux-gnu -mattr=sve < %s | FileCheck %s
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We don't want to keep these tests in their current form, instead they should be rewritten to use the sret forms explicitly. Because after this patch, we don't support code-gen for the old forms any more (when AutoUpgrade isn't run).

If you want to test the transformation from the old wide-vector -> sret forms, you can create some new LLVM IR -> LLVM IR tests by running only the auto-upgrade pass.


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Comment at: llvm/test/CodeGen/AArch64/sve-intrinsics-ldN-reg+imm-addr-mode.ll:405-407
+; CHECK-NEXT:    mov z0.d, z2.d
+; CHECK-NEXT:    mov z1.d, z2.d
+; CHECK-NEXT:    mov z3.d, z2.d
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This doesn't look right, you seem to have heard-coded the index for the extractvalue.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D133025/new/

https://reviews.llvm.org/D133025