[PATCH] D132957: [AMDGPU][MC][GFX11][NFC] Update tests for VOP3P.DPP instructions

[Dmitry Preobrazhensky via Phabricator via llvm-commits]

dp added inline comments.


================
Comment at: llvm/test/MC/AMDGPU/gfx11_asm_vop3p_dpp16.s:20
+
+// FIXME: it is not clear if op_sel may be used with these instructions. SPG requires op_sel=0 and op_sel_hi=7.
+
----------------
Joe_Nash wrote:
> I'm not sure where you're getting op_sel_hi=7 for v_fma_mix* instructions. From my reading of the spec and comparison with sp3, all values of op_sel and op_sel_hi are supported. The behavior is non-standard for mix opcodes, but the values should be accepted. 
> Does your observation have anything to do with dpp? Both dpp and non-dpp version should behave the same and allow all values of op_sel. 
I remember that SPG stated the following at some point: 

    When using DPP with VOP3/VOP3P, the OPSEL must be set such that the low result only uses low inputs, and the high result only uses high inputs.

I always thought that this was a suspicious statement, but see the original tests `gfx11_asm_vop3p_dpp8.s` below, they stated essentially the same:

    // For test purpose only. OP_SEL has to be set to all 0 and OP_SEL_HI has to be set to all 1


================
Comment at: llvm/test/MC/AMDGPU/gfx11_asm_vop3p_dpp8.s:13
 
 // For test purpose only. OP_SEL has to be set to all 0 and OP_SEL_HI has to be set to all 1
 v_fma_mixlo_f16 v0, abs(v1), -v2, abs(v3) op_sel:[1,0,0] op_sel_hi:[1,0,0] dpp8:[2,2,2,2,4,4,4,4]
----------------
Here is the original comment.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D132957/new/

https://reviews.llvm.org/D132957