[PATCH] D132957: [AMDGPU][MC][GFX11][NFC] Update tests for VOP3P.DPP instructions

[Joe Nash via Phabricator via llvm-commits]

Joe_Nash added inline comments.


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Comment at: llvm/test/MC/AMDGPU/gfx11_asm_vop3p_dpp16.s:8
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+// FIXME: it looks like the encoding of DOT instructions is incorrect. SP3 sets op_sel_hi to 0x7.
+
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I agree something is weird here with v_dot2_f32_f16 and v_dot2_f32_bf16, I will try to clarify the desired behavior.


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Comment at: llvm/test/MC/AMDGPU/gfx11_asm_vop3p_dpp16.s:20
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+// FIXME: it is not clear if op_sel may be used with these instructions. SPG requires op_sel=0 and op_sel_hi=7.
+
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I'm not sure where you're getting op_sel_hi=7 for v_fma_mix* instructions. From my reading of the spec and comparison with sp3, all values of op_sel and op_sel_hi are supported. The behavior is non-standard for mix opcodes, but the values should be accepted. 
Does your observation have anything to do with dpp? Both dpp and non-dpp version should behave the same and allow all values of op_sel. 


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D132957/new/

https://reviews.llvm.org/D132957