[PATCH] D131959: [AMDGPU] Fix SDST operand of V_DIV_SCALE to always be VCC

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp:1010
+    auto *RI = ST->getRegisterInfo();
+    const auto VCC = ST->isWave32() ? AMDGPU::VCC_LO : AMDGPU::VCC;
+    const auto Reg =
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TRI->getVCC().


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Comment at: llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp:1012
+    const auto Reg =
+        CurDAG->getMachineFunction().addLiveIn(VCC, RI->getWaveMaskRegClass());
+    CurDAG->ReplaceAllUsesOfValueWith(
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Is this really needed?


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Comment at: llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp:940
   auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opc), Dst0)
-    .addDef(Dst1)
-    .addImm(0)     // $src0_modifiers
-    .addUse(Src0)  // $src0
-    .addImm(0)     // $src1_modifiers
-    .addUse(Denom) // $src1
-    .addImm(0)     // $src2_modifiers
-    .addUse(Numer) // $src2
-    .addImm(0)     // $clamp
-    .addImm(0);    // $omod
+                 .addImm(0)     // $src0_modifiers
+                 .addUse(Src0)  // $src0
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Tabs.


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Comment at: llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp:957
+  // to that register so the value can still be used.
+  MIB = BuildMI(*MBB, MIB->getNextNode(), DL, TII.get(AMDGPU::COPY), Dst1)
+            .addReg(STI.isWave32() ? AMDGPU::VCC_LO : AMDGPU::VCC);
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MIB->getNextNode() looks suspicious.


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Comment at: llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp:958
+  MIB = BuildMI(*MBB, MIB->getNextNode(), DL, TII.get(AMDGPU::COPY), Dst1)
+            .addReg(STI.isWave32() ? AMDGPU::VCC_LO : AMDGPU::VCC);
+  MRI->setRegClass(Dst1, TRI.getWaveMaskRegClass());
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TRI.getVCC().


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Comment at: llvm/test/CodeGen/AMDGPU/frem.ll:2341
 ; SI:       ; %bb.0:
-; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; SI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
-; SI-NEXT:    s_mov_b32 s3, 0xf000
-; SI-NEXT:    s_mov_b32 s2, -1
+; SI-NEXT:    s_mov_b64 s[2:3], vcc
+; SI-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
----------------
What happened here?


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Comment at: llvm/test/MC/AMDGPU/gfx10_asm_vop3.s:6796
 
-v_div_scale_f32 v5, s0, v1, v2, v3
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0x0e,0x04]
----------------
Replace s[0:1]/s0 with vcc/vcc_lo


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Comment at: llvm/test/MC/AMDGPU/gfx7_asm_vop3_e64.s:8815
 v_div_scale_f32 v5, vcc, v1, v2, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0x0e,0x04]
+// CHECK: [0x05,0x00,0xda,0xd2,0x01,0x05,0x0e,0x04]
 
----------------
Encoding is wrong.


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Comment at: llvm/test/MC/AMDGPU/vop3.s:411
 v_div_scale_f64  v[24:25], vcc, v[22:23], v[22:23], v[20:21]
-// SICI: v_div_scale_f64 v[24:25], vcc, v[22:23], v[22:23], v[20:21] ; encoding: [0x18,0x6a,0xdc,0xd2,0x16,0x2d,0x52,0x04]
+// SICI: v_div_scale_f64 v[24:25], vcc, v[22:23], v[22:23], v[20:21] ; encoding: [0x18,0x00,0xdc,0xd2,0x16,0x2d,0x52,0x04]
 // VI:   v_div_scale_f64 v[24:25], vcc, v[22:23], v[22:23], v[20:21] ; encoding: [0x18,0x6a,0xe1,0xd1,0x16,0x2d,0x52,0x04]
----------------
Ditto.


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Comment at: llvm/test/MC/AMDGPU/wave32.s:386
 
-v_div_scale_f32 v2, s2, v0, v0, v2
-// GFX1032: v_div_scale_f32 v2, s2, v0, v0, v2 ; encoding: [0x02,0x02,0x6d,0xd5,0x00,0x01,0x0a,0x04]
-// GFX1064-ERR: :[[@LINE-2]]:21: error: invalid operand for instruction
+v_div_scale_f32 v2, vcc, v0, v0, v2
+// GFX1032-ERR: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
----------------
Please keep checks order so it is easy to see changes.


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Comment at: llvm/test/MC/AMDGPU/wave_any.s:201
 
-v_div_scale_f32 v2, s2, v0, v0, v2
-// GFX10: v_div_scale_f32 v2, s2, v0, v0, v2 ; encoding: [0x02,0x02,0x6d,0xd5,0x00,0x01,0x0a,0x04]
+v_div_scale_f32 v2, vcc, v0, v0, v2
+// GFX10: v_div_scale_f32_e64 v2, vcc, v0, v0, v2 ; encoding: [0x02,0x6a,0x6d,0xd5,0x00,0x01,0x0a,0x04]
----------------
Ditto.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131959/new/

https://reviews.llvm.org/D131959