[PATCH] D132771: [RISCV] Apply DeMorgan to (beqz (and/or (seteq), (xor Z, 1))) to remove the xor.

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Aug 29 12:02:10 PDT 2022


craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:9143
 
+// Invert (and/or (set cc X, Y), (xor X, 1)) to (or/and (set !cc X, Y)), Z) if
+// the result is used as the conditon of a br_cc or select_cc we can invert,
----------------
reames wrote:
> I think you meant xor Z, 1?
I did indeed.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:9165
+
+  // If the condition is an And, SimplifyDemandedBits may have changed
+  // (xor Z, 1) to (not Z).
----------------
reames wrote:
> This bit of logic seems like it's getting repeated a bunch, can we factor out a utility?  Something like matchLogicalNot?
Just the constant value checking? I don't think `matchLogicalNot` is a good name for that. I'm not sure what a good name is. `isOneOrAllOnes` with a bool for `AllowAllOnes`?


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  https://reviews.llvm.org/D132771/new/

https://reviews.llvm.org/D132771



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