[PATCH] D132771: [RISCV] Apply DeMorgan to (beqz (and/or (seteq), (xor Z, 1))) to remove the xor.

[Philip Reames via Phabricator via llvm-commits]

reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.

LGTM



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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:9143
 
+// Invert (and/or (set cc X, Y), (xor X, 1)) to (or/and (set !cc X, Y)), Z) if
+// the result is used as the conditon of a br_cc or select_cc we can invert,
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I think you meant xor Z, 1?


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:9165
+
+  // If the condition is an And, SimplifyDemandedBits may have changed
+  // (xor Z, 1) to (not Z).
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This bit of logic seems like it's getting repeated a bunch, can we factor out a utility?  Something like matchLogicalNot?


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Comment at: llvm/test/CodeGen/RISCV/setcc-logic.ll:306
+; RV32I-NEXT:    snez a1, a1
+; RV32I-NEXT:    or a0, a1, a0
+; RV32I-NEXT:    bnez a0, .LBB13_2
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As a follow up, is it worth exploiting the fact that we can skip the snez on the xor and just use the xor result as a non-boolean?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D132771/new/

https://reviews.llvm.org/D132771