[PATCH] D132798: [RISCV] Add more invertible setccs to tryDemorganOfBooleanCondition.
Philip Reames via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 29 11:35:53 PDT 2022
reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.
LGTM
================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:9210
Setcc.getOperand(1), CCVal);
+ } else if (CCVal == ISD::SETLT && isNullConstant(Setcc.getOperand(0))) {
+ // Invert (setlt 0, X) by converting to (setlt X, 1).
----------------
I think we can generalize this for any constant operand where adding one doesn't overflow? If so, mind doing that in a follow up?
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D132798/new/
https://reviews.llvm.org/D132798
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