[PATCH] D131343: [RISC-V][HWASAN] Add support for lowering HWASAN intrinsic for RISC-V

[Alexey Baturo via Phabricator via llvm-commits]

smd added a comment.

@jrtc27 sorry for the mess

In D131343#3754228 <https://reviews.llvm.org/D131343#3754228>, @jrtc27 wrote:

> This was committed without addressing all the feedback you were provided

What's the best way to fix it: would you like me to revert the commit  or address the issues in next patches?

In D131343#3754229 <https://reviews.llvm.org/D131343#3754229>, @jrtc27 wrote:

> And if you’re committing a significant chunk of code to a backend I don’t think you should be doing so without getting approval from someone who regularly works on the backend

Would you mind me adding you as a reviewer for further patches?



================
Comment at: llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll:58
+; CHECK-NEXT: jr      t1
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; NOPIC: {{.*}}
----------------
jrtc27 wrote:
> I do not understand what this comment is saying nor what the following lines are for
tbh, me neither, but this comment was added by update_llc_test_checks.py

>Surely you need UTC_ARGS
Let me try this and see if it changes anything


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131343/new/

https://reviews.llvm.org/D131343