[PATCH] D131343: [RISC-V][HWASAN] Add support for lowering HWASAN intrinsic for RISC-V

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added a comment.

And if you’re committing a significant chunk of code to a backend I don’t think you should be doing so without getting approval from someone who regularly works on the backend



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Comment at: llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll:23
+
+; CHECK: .section        .text.hot,"axG", at progbits,__hwasan_check_x10_2_short,comdat
+; CHECK-NEXT: .type   __hwasan_check_x10_2_short, at function
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Surely you need UTC_ARGS 
: —disable/—enable around this so it persists across reruns of update_llc_test_checks.py?


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Comment at: llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll:58
+; CHECK-NEXT: jr      t1
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; NOPIC: {{.*}}
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I do not understand what this comment is saying nor what the following lines are for


Repository:
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  https://reviews.llvm.org/D131343/new/

https://reviews.llvm.org/D131343