[PATCH] D132671: [RISCV] Teach combineDeMorganOfBoolean to handle (and (xor X, 1), (not Y)).

[Craig Topper via Phabricator via llvm-commits]

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SimplifyDemandedBits tries to agressively turn xor immediates into -1
to match a 'not' instruction. In this case, because X is a boolean, the
upper bits of (xor X, 1) are known to be 0. Because this is an AND
instruction, that means those bits aren't demanded from the other
operand, and thus SimplifyDemandedBits can turn (xor Y, 1) to (not Y).

We need to detect that this has happened to enable the DeMorgan
optimization. To do this we allow one of the xors to use -1 when
the outer operation is And.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D132671

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/double-previous-failure.ll
  llvm/test/CodeGen/RISCV/setcc-logic.ll

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