[PATCH] D132650: RISCV] : Add support for simm10_lsb0000nonzero operand
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Thu Aug 25 06:18:54 PDT 2022
MarkGoncharovAl created this revision.
MarkGoncharovAl added reviewers: craig.topper, shiva0217, sameer.abuasal.
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Running on RISCV machine llvm-exegesis I faced with trouble: can't measure C_ADDI16SP, beacuse immediate has type simm10_lsb0000nonzero.
Patch adds support for processing this immediate operand type.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D132650
Files:
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoC.td
Index: llvm/lib/Target/RISCV/RISCVInstrInfoC.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -204,6 +204,8 @@
let ParserMatchClass = SImmAsmOperand<10, "Lsb0000NonZero">;
let EncoderMethod = "getImmOpValue";
let DecoderMethod = "decodeSImmNonZeroOperand<10>";
+ let OperandType = "OPERAND_SIMM10_LSB0000_NONZERO";
+ let OperandNamespace = "RISCVOp";
let MCOperandPredicate = [{
int64_t Imm;
if (!MCOp.evaluateAsConstantImm(Imm))
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1165,6 +1165,9 @@
CASE_OPERAND_UIMM(12)
CASE_OPERAND_UIMM(20)
// clang-format on
+ case RISCVOp::OPERAND_SIMM10_LSB0000_NONZERO:
+ Ok = isShiftedInt<6, 4>(Imm) && (Imm != 0);
+ break;
case RISCVOp::OPERAND_ZERO:
Ok = Imm == 0;
break;
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
===================================================================
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -228,6 +228,7 @@
OPERAND_SIMM5_PLUS1,
OPERAND_SIMM6,
OPERAND_SIMM6_NONZERO,
+ OPERAND_SIMM10_LSB0000_NONZERO,
OPERAND_SIMM12,
OPERAND_SIMM12_LSB00000,
OPERAND_UIMM20,
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