[PATCH] D132373: [RISCV] When ISD::SETUGT && Imm == -1, processed before lowering

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Aug 24 09:06:05 PDT 2022


craig.topper added a comment.

In D132373#3745011 <https://reviews.llvm.org/D132373#3745011>, @Miss_Grape wrote:

> In D132373#3739786 <https://reviews.llvm.org/D132373#3739786>, @craig.topper wrote:
>
>> In D132373#3739683 <https://reviews.llvm.org/D132373#3739683>, @reames wrote:
>>
>>> Please follow LLVM development policies.  Add a description of the change, and tests which demonstrate it.
>>
>> This is removing code that I added out of paranoia. I agree it should never happen.
>>
>> At the very least it needs a comment and an assert.
>
> I think this scenario has already been processed in the previous optimization stage. What do you think would be more appropriate to change?

If you want to remove this code I suggest we replace with

  // -1 u> X should have been replaced with false
  assert((CCVal != ISD::SETUGT || Imm != -1) && "Missing canonicalization");


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D132373/new/

https://reviews.llvm.org/D132373



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