[llvm] 07a700f - [RISCV] Add zihintntl compressed instructions
via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 23 23:29:16 PDT 2022
Author: Alex
Date: 2022-08-24T14:29:02+08:00
New Revision: 07a700f814bf3799b865f265d01327d2b3bbc2c4
URL: https://github.com/llvm/llvm-project/commit/07a700f814bf3799b865f265d01327d2b3bbc2c4
DIFF: https://github.com/llvm/llvm-project/commit/07a700f814bf3799b865f265d01327d2b3bbc2c4.diff
LOG: [RISCV] Add zihintntl compressed instructions
Add zihintntl compressed instructions and some files related to zihintntl.
This patch is base on {D121670}.
Reviewed By: kito-cheng
Differential Revision: https://reviews.llvm.org/D121779
Added:
llvm/test/MC/RISCV/rv32zihintntl-invalid.s
llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
llvm/test/MC/RISCV/rv32zihintntlc-valid.s
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoC.td
llvm/test/MC/RISCV/attribute-arch.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
index fc25504eb540b..f3ca460c15caf 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -695,6 +695,13 @@ def C_SRAI64_HINT : RVInst16CI<0b100, 0b01, (outs GPRC:$rd_wb),
// Assembler Pseudo Instructions
//===----------------------------------------------------------------------===//
+let Predicates = [HasStdExtC, HasRVCHints, HasStdExtZihintntl] in {
+def : InstAlias<"c.ntl.p1", (C_ADD_HINT X0, X2)>;
+def : InstAlias<"c.ntl.pall", (C_ADD_HINT X0, X3)>;
+def : InstAlias<"c.ntl.s1", (C_ADD_HINT X0, X4)>;
+def : InstAlias<"c.ntl.all", (C_ADD_HINT X0, X5)>;
+} // Predicates = [HasStdExtC, HasRVCHints, HasStdExtZihintntl]
+
let EmitPriority = 0 in {
let Predicates = [HasStdExtCOrZca] in {
def : InstAlias<"c.lw $rd, (${rs1})", (C_LW GPRC:$rd, GPRC:$rs1, 0)>;
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index aec62be0d0a79..9b9eb1c093151 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -185,6 +185,12 @@
.attribute arch, "rv32i_zk1p0"
# CHECK: attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
+.attribute arch, "rv32izihintntl0p2"
+# CHECK: attribute 5, "rv32i2p0_zihintntl0p2"
+
+.attribute arch, "rv32iczihintntl0p2"
+# CHECK: attribute 5, "rv32i2p0_c2p0_zihintntl0p2"
+
.attribute arch, "rv32if_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
# CHECK: attribute 5, "rv32i2p0_f2p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
diff --git a/llvm/test/MC/RISCV/rv32zihintntl-invalid.s b/llvm/test/MC/RISCV/rv32zihintntl-invalid.s
new file mode 100644
index 0000000000000..7d4a0ffe1bd4e
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32zihintntl-invalid.s
@@ -0,0 +1,13 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zihintntl < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zihintntl < %s 2>&1 | FileCheck %s
+
+ntl.p1 1 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ntl.pall 2 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
+ntl.s1 3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ntl.all 4 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+
+ntl.p1 t0, t1 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ntl.pall t0, t1 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
+ntl.s1 t0, t1 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ntl.all t0, t1 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+
diff --git a/llvm/test/MC/RISCV/rv32zihintntlc-invalid.s b/llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
new file mode 100644
index 0000000000000..732d7cf78fd0c
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
@@ -0,0 +1,13 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zihintntl,+c < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zihintntl,+c < %s 2>&1 | FileCheck %s
+
+c.ntl.p1 1 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
+c.ntl.pall 2 # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
+c.ntl.s1 3 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
+c.ntl.all 4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+
+c.ntl.p1 t0, t1 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
+c.ntl.pall t0, t1 # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
+c.ntl.s1 t0, t1 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
+c.ntl.all t0, t1 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+
diff --git a/llvm/test/MC/RISCV/rv32zihintntlc-valid.s b/llvm/test/MC/RISCV/rv32zihintntlc-valid.s
new file mode 100644
index 0000000000000..329122e2d5083
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32zihintntlc-valid.s
@@ -0,0 +1,52 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl,+c -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl,+c -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zihintntl,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zihintntl,+c -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zihintntl,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zihintntl,+c -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: not llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
+# RUN: not llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
+
+# CHECK-ASM-AND-OBJ: ntl.p1
+# CHECK-ASM: encoding: [0x33,0x00,0x20,0x00]
+ntl.p1
+
+# CHECK-ASM-AND-OBJ: ntl.pall
+# CHECK-ASM: encoding: [0x33,0x00,0x30,0x00]
+ntl.pall
+
+# CHECK-ASM-AND-OBJ: ntl.s1
+# CHECK-ASM: encoding: [0x33,0x00,0x40,0x00]
+ntl.s1
+
+# CHECK-ASM-AND-OBJ: ntl.all
+# CHECK-ASM: encoding: [0x33,0x00,0x50,0x00]
+ntl.all
+
+# CHECK-ASM-AND-OBJ: c.ntl.p1
+# CHECK-ASM: encoding: [0x0a,0x90]
+# CHECK-NO-C: error: instruction requires the following: 'C' (Compressed Instructions)
+# CHECK-NO-C-NEXT: c.ntl.p1
+c.ntl.p1
+
+# CHECK-ASM-AND-OBJ: c.ntl.pall
+# CHECK-ASM: encoding: [0x0e,0x90]
+# CHECK-NO-C: error: instruction requires the following: 'C' (Compressed Instructions)
+# CHECK-NO-C-NEXT: c.ntl.pall
+c.ntl.pall
+
+# CHECK-ASM-AND-OBJ: c.ntl.s1
+# CHECK-ASM: encoding: [0x12,0x90]
+# CHECK-NO-C: error: instruction requires the following: 'C' (Compressed Instructions)
+# CHECK-NO-C-NEXT: c.ntl.s1
+c.ntl.s1
+
+# CHECK-ASM-AND-OBJ: c.ntl.all
+# CHECK-ASM: encoding: [0x16,0x90]
+# CHECK-NO-C: error: instruction requires the following: 'C' (Compressed Instructions)
+# CHECK-NO-C-NEXT: c.ntl.all
+c.ntl.all
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