[PATCH] D132529: [AArch64] Fix sched model for tsv110

[Allen zhong via Phabricator via llvm-commits]

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Update three changes:

1. Two store function units cannot be executed concurrently.
2. Integer ADD and SUB instructions have different latencies and processor resource usage (pipeline) when they have a shift of zero vs. non-zero, refer to D8043 <https://reviews.llvm.org/D8043>
3. The throughout of scalar DIV.


https://reviews.llvm.org/D132529

Files:
  llvm/lib/Target/AArch64/AArch64SchedTSV110.td
  llvm/test/tools/llvm-mca/AArch64/HiSilicon/tsv110-basic-instructions.s

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