[PATCH] D132482: RISCV: permit unaligned nop-slide padding emission

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


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Comment at: llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp:366
+  // section (otherwise we have unaligned instructions, and thus have far
+  // bigger problems), so just write zeros instead.  This also may occur for
+  // non-standard data sections which are not declared and thus get detected as
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compnerd wrote:
> jrtc27 wrote:
> > IALIGN; C changes this from 4 to 2
> Sorry, I don't understand what you mean by `IALIGN`.  Yeah, I should fix that to say "4-byte  (or 2-byte under C)".
>From the RISC-V unprivileged spec:

> We use the term IALIGN (measured in bits) to refer to the instruction-address alignment constraint the implementation enforces. IALIGN is 32 bits in the base ISA, but some ISA extensions, including the compressed ISA extension, relax IALIGN to 16 bits. IALIGN may not take on any value other than 16 or 32.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D132482/new/

https://reviews.llvm.org/D132482