[PATCH] D132436: [AMDGPU][SIFrameLowering] Unify custom SGPR spill saves and restores (NFC)

[Christudasan Devadasan via Phabricator via llvm-commits]

cdevadas added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIFrameLowering.cpp:269
+
+  void copyToScratchSGPR(Register DstReg) const {
+    const TargetRegisterClass *RC = TRI.getPhysRegClass(DstReg);
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sebastian-ne wrote:
> cdevadas wrote:
> > sebastian-ne wrote:
> > > Why does this code split the copies into SubRegs and copyFromScratchSGPR doesn’t?
> > For the purpose of emitting CFI directives for each copy. There is no CFI emitted in the epilogue.
> > There is more coming in the downstream version of this patch.
> Hm, does that mean CFI cannot represent register pairs?
> If so, can we emit a single copy instruction for the super register and multiple CFI instructions for the subregisters?
Sure, we will get the benefit for 64-bit copies as we have the 'S_MOV_B64' instruction. But for the CFI emission, we need composite expressions for register pairs. @scott.linder to comment about its impact.
For now, I will change the code to emit a single COPY instruction for the register pair while retaining separate CFI instructions for equivalent SubRegs.


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  https://reviews.llvm.org/D132436/new/

https://reviews.llvm.org/D132436