[PATCH] D131254: [AMDGPU][GISel] Enable Selection of ADD3 for G_PTR_ADD

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/VOP3Instructions.td:597
 
-class ThreeOp_i32_Pats <SDPatternOperator op1, SDPatternOperator op2, Instruction inst> : GCNPat <
-  // This matches (op2 (op1 i32:$src0, i32:$src1), i32:$src2) with conditions.
-  (ThreeOpFrag<op1, op2> i32:$src0, i32:$src1, i32:$src2),
-  (inst VSrc_b32:$src0, VSrc_b32:$src1, VSrc_b32:$src2)
->;
+class ThreeOp_i32_Pats <SDPatternOperator op1, SDPatternOperator op2, Instruction inst, list<ValueType> types = [i32, i32, i32]> 
+  : GCNPat <(ThreeOpFrag<op1, op2> types[0]:$src0, types[1]:$src1, types[2]:$src2),
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Remove "_i32_" from the name now that it can handle other types too?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131254/new/

https://reviews.llvm.org/D131254