[PATCH] D132394: [NFC][PowerPC] Clean up a couple of lambdas from the PPCMIPeephole.

[Stefan Pintilie via Phabricator via llvm-commits]

stefanp created this revision.
stefanp added a reviewer: nemanjai.
Herald added subscribers: shchenz, kbarton, hiraditya.
Herald added a project: All.
stefanp requested review of this revision.
Herald added a project: LLVM.

There were two sections of code that had a lot of lambdas and in the patch
D40554 <https://reviews.llvm.org/D40554> it was suggested that we clean them up as a follow-up NFC patch.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D132394

Files:
  llvm/lib/Target/PowerPC/PPCMIPeephole.cpp


Index: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
+++ llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
@@ -778,28 +778,23 @@
           break;
 
         MachineInstr *SrcMI = MRI->getVRegDef(NarrowReg);
+        unsigned SrcOpcode = SrcMI->getOpcode();
         // If we've used a zero-extending load that we will sign-extend,
         // just do a sign-extending load.
-        if (SrcMI->getOpcode() == PPC::LHZ ||
-            SrcMI->getOpcode() == PPC::LHZX) {
+        if (SrcOpcode == PPC::LHZ || SrcOpcode == PPC::LHZX) {
           if (!MRI->hasOneNonDBGUse(SrcMI->getOperand(0).getReg()))
             break;
-          auto is64Bit = [](unsigned Opcode) {
-            return Opcode == PPC::EXTSH8 || Opcode == PPC::EXTSH8_32_64;
-          };
-          auto isXForm = [] (unsigned Opcode) {
-            return Opcode == PPC::LHZX;
-          };
-          auto getSextLoadOp = [] (bool is64Bit, bool isXForm) {
-            if (is64Bit)
-              if (isXForm) return PPC::LHAX8;
-              else         return PPC::LHA8;
-            else
-              if (isXForm) return PPC::LHAX;
-              else         return PPC::LHA;
-          };
-          unsigned Opc = getSextLoadOp(is64Bit(MI.getOpcode()),
-                                       isXForm(SrcMI->getOpcode()));
+          // Determine the new opcode. We need to make sure that if the original
+          // instruction has a 64 bit opcode we keep using a 64 bit opcode.
+          // Likewise if the source is X-Form the new opcode should also be
+          // X-Form.
+          unsigned Opc = PPC::LHA;
+          if (MI.getOpcode() == PPC::EXTSH8 ||
+              MI.getOpcode() == PPC::EXTSH8_32_64) {
+            if (SrcOpcode == PPC::LHZX) Opc = PPC::LHAX8;
+            else                        Opc = PPC::LHA8;
+          } else if (SrcOpcode == PPC::LHZX)
+            Opc = PPC::LHAX;
 
           LLVM_DEBUG(dbgs() << "Zero-extending load\n");
           LLVM_DEBUG(SrcMI->dump());
@@ -823,26 +818,12 @@
           break;
 
         MachineInstr *SrcMI = MRI->getVRegDef(NarrowReg);
+        unsigned SrcOpcode = SrcMI->getOpcode();
         // If we've used a zero-extending load that we will sign-extend,
         // just do a sign-extending load.
-        if (SrcMI->getOpcode() == PPC::LWZ ||
-            SrcMI->getOpcode() == PPC::LWZX) {
+        if (SrcOpcode == PPC::LWZ || SrcOpcode == PPC::LWZX) {
           if (!MRI->hasOneNonDBGUse(SrcMI->getOperand(0).getReg()))
             break;
-          auto is64Bit = [] (unsigned Opcode) {
-            return Opcode == PPC::EXTSW || Opcode == PPC::EXTSW_32_64;
-          };
-          auto isXForm = [] (unsigned Opcode) {
-            return Opcode == PPC::LWZX;
-          };
-          auto getSextLoadOp = [] (bool is64Bit, bool isXForm) {
-            if (is64Bit)
-              if (isXForm) return PPC::LWAX;
-              else         return PPC::LWA;
-            else
-              if (isXForm) return PPC::LWAX_32;
-              else         return PPC::LWA_32;
-          };
 
           // The transformation from a zero-extending load to a sign-extending
           // load is only legal when the displacement is a multiple of 4.
@@ -860,8 +841,17 @@
               IsWordAligned = true;
           }
 
-          unsigned Opc = getSextLoadOp(is64Bit(MI.getOpcode()),
-                                       isXForm(SrcMI->getOpcode()));
+          // Determine the new opcode. We need to make sure that if the original
+          // instruction has a 64 bit opcode we keep using a 64 bit opcode.
+          // Likewise if the source is X-Form the new opcode should also be
+          // X-Form.
+          unsigned Opc = PPC::LWA_32;
+          if (MI.getOpcode() == PPC::EXTSW ||
+              MI.getOpcode() == PPC::EXTSW_32_64) {
+            if (SrcOpcode == PPC::LWZX) Opc = PPC::LWAX;
+            else                        Opc = PPC::LWA;
+          } else if (SrcOpcode == PPC::LWZX)
+            Opc = PPC::LWAX_32;
 
           if (!IsWordAligned && (Opc == PPC::LWA || Opc == PPC::LWA_32))
             break;


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D132394.454551.patch
Type: text/x-patch
Size: 4214 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220822/4f39e02b/attachment.bin>