[PATCH] D132373: [RISCV] When ISD::SETUGT && Imm == -1, processed before lowering

[LiqinWeng via Phabricator via llvm-commits]

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https://reviews.llvm.org/D132373

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp


Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -3636,10 +3636,6 @@
       if (isa<ConstantSDNode>(RHS)) {
         int64_t Imm = cast<ConstantSDNode>(RHS)->getSExtValue();
         if (Imm != 0 && isInt<12>((uint64_t)Imm + 1)) {
-          // If this is an unsigned compare and the constant is -1, incrementing
-          // the constant would change behavior. The result should be false.
-          if (CCVal == ISD::SETUGT && Imm == -1)
-            return DAG.getConstant(0, DL, VT);
           // Using getSetCCSwappedOperands will convert SET(U)GT->SET(U)LT.
           CCVal = ISD::getSetCCSwappedOperands(CCVal);
           SDValue SetCC = DAG.getSetCC(


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