[PATCH] D130993: [AArch64][SVE] Extend LD1RQ ISel patterns to cover missing addressing modes

[Matt Devereau via Phabricator via llvm-commits]

MattDevereau updated this revision to Diff 454458.
MattDevereau added a comment.

Multiclassed more LD1RQ patterns into ld1rq_pat
Added AddedComplexity to immediate patterns to prevent scalar + immediate cases regressing to scalar + scalar(mov)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130993/new/

https://reviews.llvm.org/D130993

Files:
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll
  llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-sve-instructions.s

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