[PATCH] D132205: [llvm-tblgen] CodeGenSchedModels::hasReadOfWrite gets wrong predication result

[Zixuan Wu via Phabricator via llvm-commits]

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CodeGenSchedModels::hasReadOfWrite tries to predicate whether the WriteDef is contained in the list of ValidWrites of someone ProcReadAdvance, so that WriteID of WriteDef can be compressed and reusable.

It tries to iterate all ProcReadAdvance entry, but not all ProcReadAdvance defs also inherit from SchedRead. Some ProcReadAdvances are defined by `ReadAdvance`.

  // A processor may define a ReadAdvance associated with a SchedRead
  // to reduce latency of a prior write by N cycles. A negative advance
  // effectively increases latency, which may be used for cross-domain
  // stalls.
  //
  // A ReadAdvance may be associated with a list of SchedWrites
  // to implement pipeline bypass. The Writes list may be empty to
  // indicate operands that are always read this number of Cycles later
  // than a normal register read, allowing the read's parent instruction
  // to issue earlier relative to the writer.
  class ReadAdvance<SchedRead read, int cycles, list<SchedWrite> writes = []>
    : ProcReadAdvance<cycles, writes> {
    SchedRead ReadType = read;
  }
  
  // Directly associate a new SchedRead type with a delay and optional
  // pipeline bypass. For use with InstRW or ItinRW.
  class SchedReadAdvance<int cycles, list<SchedWrite> writes = []> : SchedRead,
    ProcReadAdvance<cycles, writes>;

So it's not complete to enumerate all ProcReadAdvances if just iterate all SchedReads.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D132205

Files:
  llvm/utils/TableGen/CodeGenSchedule.cpp


Index: llvm/utils/TableGen/CodeGenSchedule.cpp
===================================================================
--- llvm/utils/TableGen/CodeGenSchedule.cpp
+++ llvm/utils/TableGen/CodeGenSchedule.cpp
@@ -734,14 +734,12 @@
 }
 
 bool CodeGenSchedModels::hasReadOfWrite(Record *WriteDef) const {
-  for (const CodeGenSchedRW &Read : SchedReads) {
-    Record *ReadDef = Read.TheDef;
-    if (!ReadDef || !ReadDef->isSubClassOf("ProcReadAdvance"))
-      continue;
-
-    RecVec ValidWrites = ReadDef->getValueAsListOfDefs("ValidWrites");
-    if (is_contained(ValidWrites, WriteDef)) {
-      return true;
+  for (auto& ProcModel : ProcModels) {
+    const RecVec &RADefs = ProcModel.ReadAdvanceDefs;
+    for (auto& RADef : RADefs) {
+      RecVec ValidWrites = RADef->getValueAsListOfDefs("ValidWrites");
+      if (is_contained(ValidWrites, WriteDef))
+        return true;
     }
   }
   return false;


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