[PATCH] D131841: [RISCV] Merge vmerge.vvm and unmasked intrinsic with VLMAX vector length.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:2677
+    // are dependent on Merge. VLMAX should be lowered to (XLenVT -1).
+    if (TrueVL != VL && !isAllOnesConstant(TrueVL))
       continue;
----------------
This is incorrect if the True opcode can raise a floating point exception. Applying the mask could lose an exception that should occur even if the result is discarded.

I think we need to look up the MayRaiseException property from the MCInstrDesc entry for the opcode. If it is has that properly, we need to check that the hasNoFPExcept bit in the SDNodeFlags is set before doing this combine.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131841/new/

https://reviews.llvm.org/D131841