[PATCH] D132122: AArch64 SVE: add sve patterns to make use of predicated smin, umin, smax, and umax instructions, add ll test file for the new patterns

Thu Aug 18 06:03:49 PDT 2022

david-arm edited reviewers, added: kmclaughlin; removed: sdesmalen.
david-arm added a comment.

Thanks for this @hassnaa-arm, it looks like a useful addition to the patterns! I just spotted an issue with the test output for elements other than i32.

================
Comment at: llvm/test/CodeGen/AArch64/sve-min-max-pred.ll:13
+; CHECK-LABEL: smax_i8:
+; CHECK: smax z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT: ret
----------------
I don't quite understand what's going on here, but this doesn't look right I'm afraid! The vector elements are 8-bits so I was expecting to see this instead:

  ; CHECK: smax z0.b, p0/m, z0.b, z1.b

It's the same problem for all the smax/smin/umax/umin examples here where the element type != i32.

================
Comment at: llvm/test/CodeGen/AArch64/sve-min-max-pred.ll:31
+; CHECK-LABEL: smax_i32:
+; CHECK: smax z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT: ret
----------------
This looks right!

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D132122/new/

https://reviews.llvm.org/D132122