[PATCH] D132107: [DAGCombiner][NFC] Remove extra brackets.
WangLian via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 18 00:38:45 PDT 2022
Jimerlife updated this revision to Diff 453548.
Jimerlife retitled this revision from "[DAGCombiner][NFC] Remove extra brackets and add use check for VSCALE." to "[DAGCombiner][NFC] Remove extra brackets.".
Jimerlife edited the summary of this revision.
Jimerlife added a comment.
address comment
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D132107/new/
https://reviews.llvm.org/D132107
Files:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2672,9 +2672,9 @@
}
// fold a+vscale(c1)+vscale(c2) -> a+vscale(c1+c2)
- if ((N0.getOpcode() == ISD::ADD) &&
- (N0.getOperand(1).getOpcode() == ISD::VSCALE) &&
- (N1.getOpcode() == ISD::VSCALE)) {
+ if (N0.getOpcode() == ISD::ADD &&
+ N0.getOperand(1).getOpcode() == ISD::VSCALE &&
+ N1.getOpcode() == ISD::VSCALE) {
const APInt &VS0 = N0.getOperand(1)->getConstantOperandAPInt(0);
const APInt &VS1 = N1->getConstantOperandAPInt(0);
SDValue VS = DAG.getVScale(DL, VT, VS0 + VS1);
@@ -2691,9 +2691,9 @@
}
// Fold a + step_vector(c1) + step_vector(c2) to a + step_vector(c1+c2)
- if ((N0.getOpcode() == ISD::ADD) &&
- (N0.getOperand(1).getOpcode() == ISD::STEP_VECTOR) &&
- (N1.getOpcode() == ISD::STEP_VECTOR)) {
+ if (N0.getOpcode() == ISD::ADD &&
+ N0.getOperand(1).getOpcode() == ISD::STEP_VECTOR &&
+ N1.getOpcode() == ISD::STEP_VECTOR) {
const APInt &SV0 = N0.getOperand(1)->getConstantOperandAPInt(0);
const APInt &SV1 = N1->getConstantOperandAPInt(0);
APInt NewStep = SV0 + SV1;
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