[llvm] 515ece1 - [RISCV] Add MC support of RISCV Zca Extension
via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 17 21:13:44 PDT 2022
Author: WuXinlong
Date: 2022-08-18T12:13:35+08:00
New Revision: 515ece1a9005b29747e5e19bccb17f2ae3d78fb9
URL: https://github.com/llvm/llvm-project/commit/515ece1a9005b29747e5e19bccb17f2ae3d78fb9
DIFF: https://github.com/llvm/llvm-project/commit/515ece1a9005b29747e5e19bccb17f2ae3d78fb9.diff
LOG: [RISCV] Add MC support of RISCV Zca Extension
This patch adds support for part of Zc extension which will be frozen soon.
This extension is designed to continue reducing the binary size of RISC-V programs.
In this patch:
`Zca` is a subset of C extension instructions that are compatible with the Zc extension.
The spec of Zc ext is [[ https://github.com/riscv/riscv-code-size-reduction/releases | Here ]]
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D130141
Added:
Modified:
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfoC.td
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/MC/RISCV/attribute-arch.s
llvm/test/MC/RISCV/rv32c-invalid.s
llvm/test/MC/RISCV/rv32c-only-valid.s
llvm/test/MC/RISCV/rv32c-valid.s
llvm/test/MC/RISCV/rv64c-hints-valid.s
llvm/test/MC/RISCV/rv64c-invalid.s
llvm/test/MC/RISCV/rv64c-valid.s
Removed:
################################################################################
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index 80bea1a567072..524df1a2e859b 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -110,6 +110,7 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
{"zbp", RISCVExtensionVersion{0, 93}},
{"zbr", RISCVExtensionVersion{0, 93}},
{"zbt", RISCVExtensionVersion{0, 93}},
+ {"zca", RISCVExtensionVersion{0, 70}},
{"zvfh", RISCVExtensionVersion{0, 1}},
};
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index e8bff273847a3..ba3dec28a7851 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -340,6 +340,19 @@ def FeatureStdExtZk
FeatureStdExtZkr,
FeatureStdExtZkt]>;
+def FeatureExtZca
+ : SubtargetFeature<"experimental-zca", "HasStdExtZca", "true",
+ "'Zca' (part of the C extension, excluding compressed floating point loads/stores)">;
+def HasStdExtZca : Predicate<"Subtarget->hasStdExtZca()">,
+ AssemblerPredicate<(all_of FeatureExtZca),
+ "'Zca' (part of the C extension, excluding compressed floating point loads/stores)">;
+
+def HasStdExtCOrZca
+ : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZca()">,
+ AssemblerPredicate<(any_of FeatureStdExtC, FeatureExtZca),
+ "'C' (Compressed Instructions) or "
+ "'Zca' (part of the C extension, excluding compressed floating point loads/stores)">;
+
def FeatureNoRVCHints
: SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false",
"Disable RVC Hint Instructions.">;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
index cd1da4360002e..fc25504eb540b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -281,7 +281,7 @@ class CS_ALU<bits<6> funct6, bits<2> funct2, string OpcodeStr,
// Instructions
//===----------------------------------------------------------------------===//
-let Predicates = [HasStdExtC] in {
+let Predicates = [HasStdExtCOrZca] in {
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Uses = [X2] in
def C_ADDI4SPN : RVInst16CIW<0b000, 0b00, (outs GPRC:$rd),
@@ -321,7 +321,7 @@ def C_FLW : CLoad_ri<0b011, "c.flw", FPR32C, uimm7_lsb00>,
let Inst{5} = imm{6};
}
-let Predicates = [HasStdExtC, IsRV64] in
+let Predicates = [HasStdExtCOrZca, IsRV64] in
def C_LD : CLoad_ri<0b011, "c.ld", GPRC, uimm8_lsb000>,
Sched<[WriteLDD, ReadMemBase]> {
bits<8> imm;
@@ -355,7 +355,7 @@ def C_FSW : CStore_rri<0b111, "c.fsw", FPR32C, uimm7_lsb00>,
let Inst{5} = imm{6};
}
-let Predicates = [HasStdExtC, IsRV64] in
+let Predicates = [HasStdExtCOrZca, IsRV64] in
def C_SD : CStore_rri<0b111, "c.sd", GPRC, uimm8_lsb000>,
Sched<[WriteSTD, ReadStoreData, ReadMemBase]> {
bits<8> imm;
@@ -391,12 +391,12 @@ def C_ADDI_NOP : RVInst16CI<0b000, 0b01, (outs GPRX0:$rd_wb),
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCall = 1,
DecoderNamespace = "RISCV32Only_", Defs = [X1],
- Predicates = [HasStdExtC, IsRV32] in
+ Predicates = [HasStdExtCOrZca, IsRV32] in
def C_JAL : RVInst16CJ<0b001, 0b01, (outs), (ins simm12_lsb0:$offset),
"c.jal", "$offset">, Sched<[WriteJal]>;
let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
- Predicates = [HasStdExtC, IsRV64] in
+ Predicates = [HasStdExtCOrZca, IsRV64] in
def C_ADDIW : RVInst16CI<0b001, 0b01, (outs GPRNoX0:$rd_wb),
(ins GPRNoX0:$rd, simm6:$imm),
"c.addiw", "$rd, $imm">,
@@ -458,7 +458,7 @@ def C_OR : CS_ALU<0b100011, 0b10, "c.or" , GPRC>,
def C_AND : CS_ALU<0b100011, 0b11, "c.and", GPRC>,
Sched<[WriteIALU, ReadIALU, ReadIALU]>;
-let Predicates = [HasStdExtC, IsRV64] in {
+let Predicates = [HasStdExtCOrZca, IsRV64] in {
def C_SUBW : CS_ALU<0b100111, 0b00, "c.subw", GPRC>,
Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>;
def C_ADDW : CS_ALU<0b100111, 0b01, "c.addw", GPRC>,
@@ -506,7 +506,7 @@ def C_FLWSP : CStackLoad<0b011, "c.flwsp", FPR32, uimm8_lsb00>,
let Inst{3-2} = imm{7-6};
}
-let Predicates = [HasStdExtC, IsRV64] in
+let Predicates = [HasStdExtCOrZca, IsRV64] in
def C_LDSP : CStackLoad<0b011, "c.ldsp", GPRNoX0, uimm9_lsb000>,
Sched<[WriteLDD, ReadMemBase]> {
let Inst{6-5} = imm{4-3};
@@ -566,7 +566,7 @@ def C_FSWSP : CStackStore<0b111, "c.fswsp", FPR32, uimm8_lsb00>,
let Inst{8-7} = imm{7-6};
}
-let Predicates = [HasStdExtC, IsRV64] in
+let Predicates = [HasStdExtCOrZca, IsRV64] in
def C_SDSP : CStackStore<0b111, "c.sdsp", GPR, uimm9_lsb000>,
Sched<[WriteSTD, ReadStoreData, ReadMemBase]> {
let Inst{12-10} = imm{5-3};
@@ -581,13 +581,13 @@ def C_UNIMP : RVInst16<(outs), (ins), "c.unimp", "", [], InstFormatOther>,
let Inst{15-0} = 0;
}
-} // Predicates = [HasStdExtC]
+} // Predicates = [HasStdExtCOrZca]
//===----------------------------------------------------------------------===//
// HINT Instructions
//===----------------------------------------------------------------------===//
-let Predicates = [HasStdExtC, HasRVCHints], hasSideEffects = 0, mayLoad = 0,
+let Predicates = [HasStdExtCOrZca, HasRVCHints], hasSideEffects = 0, mayLoad = 0,
mayStore = 0 in
{
@@ -688,7 +688,7 @@ def C_SRAI64_HINT : RVInst16CI<0b100, 0b01, (outs GPRC:$rd_wb),
let Inst{12} = 0;
}
-} // Predicates = [HasStdExtC, HasRVCHints], hasSideEffects = 0, mayLoad = 0,
+} // Predicates = [HasStdExtCOrZca, HasRVCHints], hasSideEffects = 0, mayLoad = 0,
// mayStore = 0
//===----------------------------------------------------------------------===//
@@ -696,14 +696,14 @@ def C_SRAI64_HINT : RVInst16CI<0b100, 0b01, (outs GPRC:$rd_wb),
//===----------------------------------------------------------------------===//
let EmitPriority = 0 in {
-let Predicates = [HasStdExtC] in {
+let Predicates = [HasStdExtCOrZca] in {
def : InstAlias<"c.lw $rd, (${rs1})", (C_LW GPRC:$rd, GPRC:$rs1, 0)>;
def : InstAlias<"c.sw $rs2, (${rs1})", (C_SW GPRC:$rs2, GPRC:$rs1, 0)>;
def : InstAlias<"c.lwsp $rd, (${rs1})", (C_LWSP GPRC:$rd, SP:$rs1, 0)>;
def : InstAlias<"c.swsp $rs2, (${rs1})", (C_SWSP GPRC:$rs2, SP:$rs1, 0)>;
}
-let Predicates = [HasStdExtC, IsRV64] in {
+let Predicates = [HasStdExtCOrZca, IsRV64] in {
def : InstAlias<"c.ld $rd, (${rs1})", (C_LD GPRC:$rd, GPRC:$rs1, 0)>;
def : InstAlias<"c.sd $rs2, (${rs1})", (C_SD GPRC:$rs2, GPRC:$rs1, 0)>;
def : InstAlias<"c.ldsp $rd, (${rs1})", (C_LDSP GPRC:$rd, SP:$rs1, 0)>;
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index c135934962535..571b5a75efb5b 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -60,6 +60,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
bool HasStdExtZbr = false;
bool HasStdExtZbs = false;
bool HasStdExtZbt = false;
+ bool HasStdExtZca = false;
bool HasStdExtV = false;
bool HasStdExtZve32x = false;
bool HasStdExtZve32f = false;
@@ -166,6 +167,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
bool hasStdExtZbr() const { return HasStdExtZbr; }
bool hasStdExtZbs() const { return HasStdExtZbs; }
bool hasStdExtZbt() const { return HasStdExtZbt; }
+ bool hasStdExtZca() const { return HasStdExtZca; }
bool hasStdExtZvl() const { return ZvlLen != 0; }
bool hasStdExtZvfh() const { return HasStdExtZvfh; }
bool hasStdExtZfhmin() const { return HasStdExtZfhmin; }
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index d8c75abb8edd1..aec62be0d0a79 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -187,3 +187,6 @@
.attribute arch, "rv32if_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
# CHECK: attribute 5, "rv32i2p0_f2p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
+
+.attribute arch, "rv32izca0p70"
+# CHECK: attribute 5, "rv32i2p0_zca0p70"
diff --git a/llvm/test/MC/RISCV/rv32c-invalid.s b/llvm/test/MC/RISCV/rv32c-invalid.s
index 42a3776f0337a..166476ac682f9 100644
--- a/llvm/test/MC/RISCV/rv32c-invalid.s
+++ b/llvm/test/MC/RISCV/rv32c-invalid.s
@@ -1,5 +1,7 @@
# RUN: not llvm-mc -triple=riscv32 -mattr=+c -mattr=+no-rvc-hints < %s 2>&1 \
# RUN: | FileCheck %s
+# RUN: not llvm-mc -triple=riscv32 -mattr=+experimental-zca -mattr=+no-rvc-hints < %s 2>&1 \
+# RUN: | FileCheck %s
## GPRC
.LBB:
diff --git a/llvm/test/MC/RISCV/rv32c-only-valid.s b/llvm/test/MC/RISCV/rv32c-only-valid.s
index bbab1a1c44ba0..9409cd83eb1b0 100644
--- a/llvm/test/MC/RISCV/rv32c-only-valid.s
+++ b/llvm/test/MC/RISCV/rv32c-only-valid.s
@@ -17,7 +17,7 @@
# CHECK-OBJ: c.jal 0x7fe
# CHECK-ASM: c.jal 2046
# CHECK-ASM: encoding: [0xfd,0x2f]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
# CHECK-NO-RV32: error: instruction requires the following: RV32I Base Instruction Set{{$}}
-# CHECK-NO-RV32-AND-EXT: error: instruction requires the following: 'C' (Compressed Instructions), RV32I Base Instruction Set{{$}}
+# CHECK-NO-RV32-AND-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), RV32I Base Instruction Set{{$}}
c.jal 2046
diff --git a/llvm/test/MC/RISCV/rv32c-valid.s b/llvm/test/MC/RISCV/rv32c-valid.s
index e3ea2fe084bbc..d9c1b9caeca12 100644
--- a/llvm/test/MC/RISCV/rv32c-valid.s
+++ b/llvm/test/MC/RISCV/rv32c-valid.s
@@ -3,11 +3,21 @@
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+c < %s \
# RUN: | llvm-objdump --mattr=+c -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zca -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zca < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zca -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc %s -triple=riscv64 -mattr=+c -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c < %s \
# RUN: | llvm-objdump --mattr=+c -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zca -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zca < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zca -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# RUN: not llvm-mc -triple riscv32 \
# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
@@ -17,147 +27,147 @@
# CHECK-ASM-AND-OBJ: c.lwsp ra, 0(sp)
# CHECK-ASM: encoding: [0x82,0x40]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.lwsp ra, 0(sp)
# CHECK-ASM-AND-OBJ: c.swsp ra, 252(sp)
# CHECK-ASM: encoding: [0x86,0xdf]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.swsp ra, 252(sp)
# CHECK-ASM-AND-OBJ: c.lw a2, 0(a0)
# CHECK-ASM: encoding: [0x10,0x41]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.lw a2, 0(a0)
# CHECK-ASM-AND-OBJ: c.sw a5, 124(a3)
# CHECK-ASM: encoding: [0xfc,0xde]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.sw a5, 124(a3)
# CHECK-ASM-AND-OBJ: c.lwsp s0, 0(sp)
# CHECK-ASM: encoding: [0x02,0x44]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.lwsp x8, (x2)
# CHECK-ASM-AND-OBJ: c.swsp s0, 0(sp)
# CHECK-ASM: encoding: [0x22,0xc0]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.swsp x8, (x2)
# CHECK-ASM-AND-OBJ: c.lw s0, 0(s1)
# CHECK-ASM: encoding: [0x80,0x40]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.lw x8, (x9)
# CHECK-ASM-AND-OBJ: c.sw s0, 0(s1)
# CHECK-ASM: encoding: [0x80,0xc0]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.sw x8, (x9)
# CHECK-OBJ: c.j 0xfffff810
# CHECK-ASM: c.j -2048
# CHECK-ASM: encoding: [0x01,0xb0]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.j -2048
# CHECK-ASM-AND-OBJ: c.jr a7
# CHECK-ASM: encoding: [0x82,0x88]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.jr a7
# CHECK-ASM-AND-OBJ: c.jalr a1
# CHECK-ASM: encoding: [0x82,0x95]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.jalr a1
# CHECK-OBJ: c.beqz a3, 0xffffff16
# CHECK-ASM: c.beqz a3, -256
# CHECK-ASM: encoding: [0x81,0xd2]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.beqz a3, -256
# CHECK-OBJ: c.bnez a5, 0x116
# CHECK-ASM: c.bnez a5, 254
# CHECK-ASM: encoding: [0xfd,0xef]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.bnez a5, 254
# CHECK-ASM-AND-OBJ: c.li a7, 31
# CHECK-ASM: encoding: [0xfd,0x48]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.li a7, 31
# CHECK-ASM-AND-OBJ: c.addi a3, -32
# CHECK-ASM: encoding: [0x81,0x16]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.addi a3, -32
# CHECK-ASM-AND-OBJ: c.addi16sp sp, -512
# CHECK-ASM: encoding: [0x01,0x71]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.addi16sp sp, -512
# CHECK-ASM-AND-OBJ: c.addi16sp sp, 496
# CHECK-ASM: encoding: [0x7d,0x61]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.addi16sp sp, 496
# CHECK-ASM-AND-OBJ: c.addi4spn a3, sp, 1020
# CHECK-ASM: encoding: [0xf4,0x1f]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.addi4spn a3, sp, 1020
# CHECK-ASM-AND-OBJ: c.addi4spn a3, sp, 4
# CHECK-ASM: encoding: [0x54,0x00]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.addi4spn a3, sp, 4
# CHECK-ASM-AND-OBJ: c.slli a1, 1
# CHECK-ASM: encoding: [0x86,0x05]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.slli a1, 1
# CHECK-ASM-AND-OBJ: c.srli a3, 31
# CHECK-ASM: encoding: [0xfd,0x82]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.srli a3, 31
# CHECK-ASM-AND-OBJ: c.srai a4, 2
# CHECK-ASM: encoding: [0x09,0x87]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.srai a4, 2
# CHECK-ASM-AND-OBJ: c.andi a5, 15
# CHECK-ASM: encoding: [0xbd,0x8b]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.andi a5, 15
# CHECK-ASM-AND-OBJ: c.mv a7, s0
# CHECK-ASM: encoding: [0xa2,0x88]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.mv a7, s0
# CHECK-ASM-AND-OBJ: c.and a1, a2
# CHECK-ASM: encoding: [0xf1,0x8d]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.and a1, a2
# CHECK-ASM-AND-OBJ: c.or a2, a3
# CHECK-ASM: encoding: [0x55,0x8e]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.or a2, a3
# CHECK-ASM-AND-OBJ: c.xor a3, a4
# CHECK-ASM: encoding: [0xb9,0x8e]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.xor a3, a4
# CHECK-ASM-AND-OBJ: c.sub a4, a5
# CHECK-ASM: encoding: [0x1d,0x8f]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.sub a4, a5
# CHECK-ASM-AND-OBJ: c.nop
# CHECK-ASM: encoding: [0x01,0x00]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.nop
# CHECK-ASM-AND-OBJ: c.ebreak
# CHECK-ASM: encoding: [0x02,0x90]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.ebreak
# CHECK-ASM-AND-OBJ: c.lui s0, 1
# CHECK-ASM: encoding: [0x05,0x64]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.lui s0, 1
# CHECK-ASM-AND-OBJ: c.lui s0, 31
# CHECK-ASM: encoding: [0x7d,0x64]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.lui s0, 31
# CHECK-ASM-AND-OBJ: c.lui s0, 1048544
# CHECK-ASM: encoding: [0x01,0x74]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.lui s0, 0xfffe0
# CHECK-ASM-AND-OBJ: c.lui s0, 1048575
# CHECK-ASM: encoding: [0x7d,0x74]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.lui s0, 0xfffff
# CHECK-ASM-AND-OBJ: c.unimp
# CHECK-ASM: encoding: [0x00,0x00]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.unimp
diff --git a/llvm/test/MC/RISCV/rv64c-hints-valid.s b/llvm/test/MC/RISCV/rv64c-hints-valid.s
index db1fcfec8dbd4..6f925095cc3a7 100644
--- a/llvm/test/MC/RISCV/rv64c-hints-valid.s
+++ b/llvm/test/MC/RISCV/rv64c-hints-valid.s
@@ -3,6 +3,11 @@
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c < %s \
# RUN: | llvm-objdump -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple riscv64 -mattr=+experimental-zca -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zca < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zca -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# CHECK-ASM-AND-OBJ: c.slli zero, 63
# CHECK-ASM: encoding: [0x7e,0x10]
diff --git a/llvm/test/MC/RISCV/rv64c-invalid.s b/llvm/test/MC/RISCV/rv64c-invalid.s
index e50f48b4213a3..4d7233b4cc3df 100644
--- a/llvm/test/MC/RISCV/rv64c-invalid.s
+++ b/llvm/test/MC/RISCV/rv64c-invalid.s
@@ -1,4 +1,5 @@
# RUN: not llvm-mc -triple=riscv64 -mattr=+c < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple=riscv64 -mattr=+experimental-zca < %s 2>&1 | FileCheck %s
## GPRC
c.ld ra, 4(sp) # CHECK: :[[@LINE]]:6: error: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/rv64c-valid.s b/llvm/test/MC/RISCV/rv64c-valid.s
index d415cb1558113..cd835a9ed1ed2 100644
--- a/llvm/test/MC/RISCV/rv64c-valid.s
+++ b/llvm/test/MC/RISCV/rv64c-valid.s
@@ -3,6 +3,11 @@
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c < %s \
# RUN: | llvm-objdump --mattr=+c -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zca -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c < %s \
+# RUN: | llvm-objdump --mattr=+c -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
#
#
# RUN: not llvm-mc -triple riscv64 \
@@ -16,56 +21,56 @@
# CHECK-ASM-AND-OBJ: c.ldsp ra, 0(sp)
# CHECK-ASM: encoding: [0x82,0x60]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
# CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set{{$}}
c.ldsp ra, 0(sp)
# CHECK-ASM-AND-OBJ: c.sdsp ra, 504(sp)
# CHECK-ASM: encoding: [0x86,0xff]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
# CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set{{$}}
c.sdsp ra, 504(sp)
# CHECK-ASM-AND-OBJ: c.ld a4, 0(a3)
# CHECK-ASM: encoding: [0x98,0x62]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
# CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set{{$}}
c.ld a4, 0(a3)
# CHECK-ASM-AND-OBJ: c.sd a5, 248(a3)
# CHECK-ASM: encoding: [0xfc,0xfe]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
# CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set{{$}}
c.sd a5, 248(a3)
# CHECK-ASM-AND-OBJ: c.subw a3, a4
# CHECK-ASM: encoding: [0x99,0x9e]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
# CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set{{$}}
c.subw a3, a4
# CHECK-ASM-AND-OBJ: c.addw a0, a2
# CHECK-ASM: encoding: [0x31,0x9d]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
# CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set{{$}}
c.addw a0, a2
# CHECK-ASM-AND-OBJ: c.addiw a3, -32
# CHECK-ASM: encoding: [0x81,0x36]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
# CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set{{$}}
c.addiw a3, -32
# CHECK-ASM-AND-OBJ: c.addiw a3, 31
# CHECK-ASM: encoding: [0xfd,0x26]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
# CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set{{$}}
c.addiw a3, 31
# CHECK-ASM-AND-OBJ: c.slli s0, 63
# CHECK-ASM: encoding: [0x7e,0x14]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.slli s0, 63
# CHECK-ASM-AND-OBJ: c.srli a3, 63
# CHECK-ASM: encoding: [0xfd,0x92]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.srli a3, 63
# CHECK-ASM-AND-OBJ: c.srai a2, 63
# CHECK-ASM: encoding: [0x7d,0x96]
-# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores){{$}}
c.srai a2, 63
More information about the llvm-commits
mailing list