[PATCH] D131962: [RegisterInfoEmitter] Generate isConstantPhysReg(). NFCI

[Alex Bradbury via Phabricator via llvm-commits]

asb added a comment.

This LGTM from a RISC-V perspective and makes a lot of sense to generate from from TableGen rather than hand-coding.

I think it would be worth getting an LGTM from the AMDGPU side before landing.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131962/new/

https://reviews.llvm.org/D131962