[PATCH] D118305: [Spill2Reg][8/9] Added code generation support for 8/16bit spills/reloads in x86

[Vasileios Porpodas via Phabricator via llvm-commits]

vporpo added inline comments.


================
Comment at: llvm/lib/Target/X86/X86InstrInfo.cpp:9849
+  //   $al = ...
+  //   $xmm0 = MOVPDI2DIrr $eax
+  if (auto NewReg = getMovdCompatibleReg(SrcReg, OperationBits, TRI))
----------------
Carrot wrote:
> Does it cause partial write whole read hazard?
> 
It might, though I don't know what the overhead is. Do you know how I could 
measure it? This code shows up in the test `CodeGen/X86/spill2reg_end_to_end_8bit.ll` but it runs ~7% faster with spill2reg enabled on a skylake machine, but perhaps this is not a good test to evaluate it.

Do you think it is worth adding a flag that disables it by default?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D118305/new/

https://reviews.llvm.org/D118305