[PATCH] D118305: [Spill2Reg][8/9] Added code generation support for 8/16bit spills/reloads in x86

[Guozhi Wei via Phabricator via llvm-commits]

Carrot added inline comments.


================
Comment at: llvm/lib/Target/X86/X86InstrInfo.cpp:9849
+  //   $al = ...
+  //   $xmm0 = MOVPDI2DIrr $eax
+  if (auto NewReg = getMovdCompatibleReg(SrcReg, OperationBits, TRI))
----------------
Does it cause partial write whole read hazard?



Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D118305/new/

https://reviews.llvm.org/D118305