[PATCH] D131700: [AArch64] Add pattern for SQDML*Lv1i32_indexed

Mon Aug 15 09:04:54 PDT 2022

dmgreen added a comment.

Can you add a testcase where the extractelement is not the 0 lane? It would be good to have tests to make sure that the new pattern with non-zero offset works OK.

The moved pattern looks OK from what I can see. The input hasn't changed, just been reformatted? Just the output of it has changed? I agree that I'm not sure what the FIXME meant. Tablegen can be finicky at times.

================
Comment at: llvm/lib/Target/AArch64/AArch64InstrFormats.td:8908
+                                                (v4i16 V64:$Rm))),
+                                    VectorIndexH:$idx)))),
+            (!cast<Instruction>(NAME # v1i32_indexed)
----------------
Does this need to be 0, if we use the lowest lane in the output pattern `(EXTRACT_SUBREG  V64:$Rn, hsub)`?

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131700/new/

https://reviews.llvm.org/D131700