[PATCH] D131700: [AArch64] Add pattern for SQDML*Lv1i32_indexed

[OverMighty via Phabricator via llvm-commits]

overmighty updated this revision to Diff 452644.
overmighty edited the summary of this revision.
overmighty added a comment.

The `(v4i16 (scalar_to_vector (i32 FPR32Op:$Rn)))` part of the pattern was replaced with what it already folds into: `(v4i16 V64:$Rn)`, as in the existing pattern for the `vqdml*lh_lane*_s16` functions when given a lane index other than 0. The `(i32 FPR32Op:$Rd)` part of the result has been simplified into `FPR32Op:$Rd` too.

The existing `Pat` for `vqdml*lh_lane*_s16` with lane indexes other than 0 has been modified to use the `v1i32_indexed` instructions instead of the `v4i16_indexed` ones. I figured this was a better thing to do than ask if the FIXME comment preceding it really is an issue or not. I am not sure what that comment meant by "but an intermediate `EXTRACT_SUBREG` would be untyped."

I tried to follow the indentation style that the other DAGs in the `SIMDIndexedLongSQDMLXSDTied` multiclass seemed to have.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131700/new/

https://reviews.llvm.org/D131700

Files:
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/test/CodeGen/AArch64/arm64-vmul.ll

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