[llvm] 43a8dbc - [AVR] Use @earlyclobber instead of register scavenging
Ayke van Laethem via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 15 05:29:58 PDT 2022
Author: Ayke van Laethem
Date: 2022-08-15T14:29:38+02:00
New Revision: 43a8dbc5be8ae9d31fb86f333794e51280ea3992
URL: https://github.com/llvm/llvm-project/commit/43a8dbc5be8ae9d31fb86f333794e51280ea3992
DIFF: https://github.com/llvm/llvm-project/commit/43a8dbc5be8ae9d31fb86f333794e51280ea3992.diff
LOG: [AVR] Use @earlyclobber instead of register scavenging
The code to support the case when the register allocator has assigned
the same register to the src and the dst register operand isn't actually
needed:
* LDWRdPtr and LDDWRdPtrQ have an @earlyclobber on the output
register, so the register allocator will make sure to allocate a
different register for the output register.
* LDDWRdYQ does not have an @earlyclobber, but the pointer register is
the fixed Y register which is reserved. The register allocator won't
use reserved registers for the output value.
This removes a special case in the code that makes the pseudo
instruction expansion pass more complicated than it needs to be.
Differential Revision: https://reviews.llvm.org/D131844
Added:
Modified:
llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
Removed:
llvm/test/CodeGen/AVR/pseudo/LDWRdPtr-same-src-dst.mir
################################################################################
diff --git a/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp b/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
index a9dc9af819e6b..78592d3c39a2e 100644
--- a/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
@@ -648,45 +648,28 @@ bool AVRExpandPseudo::expand<AVR::LDWRdPtr>(Block &MBB, BlockIt MBBI) {
MachineInstr &MI = *MBBI;
Register DstLoReg, DstHiReg;
Register DstReg = MI.getOperand(0).getReg();
- Register TmpReg = 0; // 0 for no temporary register
Register SrcReg = MI.getOperand(1).getReg();
bool SrcIsKill = MI.getOperand(1).isKill();
unsigned OpLo = AVR::LDRdPtr;
unsigned OpHi = AVR::LDDRdPtrQ;
TRI->splitReg(DstReg, DstLoReg, DstHiReg);
- // Use a temporary register if src and dst registers are the same.
- if (DstReg == SrcReg)
- TmpReg = scavengeGPR8(MI);
-
- Register CurDstLoReg = (DstReg == SrcReg) ? TmpReg : DstLoReg;
- Register CurDstHiReg = (DstReg == SrcReg) ? TmpReg : DstHiReg;
+ // DstReg has an earlyclobber so the register allocator will allocate them in
+ // separate registers.
+ assert(DstReg != SrcReg && "Dst and Src registers are the same!");
// Load low byte.
- auto MIBLO = buildMI(MBB, MBBI, OpLo)
- .addReg(CurDstLoReg, RegState::Define)
- .addReg(SrcReg);
-
- // Push low byte onto stack if necessary.
- if (TmpReg)
- buildMI(MBB, MBBI, AVR::PUSHRr).addReg(TmpReg);
+ buildMI(MBB, MBBI, OpLo)
+ .addReg(DstLoReg, RegState::Define)
+ .addReg(SrcReg)
+ .setMemRefs(MI.memoperands());
// Load high byte.
- auto MIBHI = buildMI(MBB, MBBI, OpHi)
- .addReg(CurDstHiReg, RegState::Define)
- .addReg(SrcReg, getKillRegState(SrcIsKill))
- .addImm(1);
-
- if (TmpReg) {
- // Move the high byte into the final destination.
- buildMI(MBB, MBBI, AVR::MOVRdRr, DstHiReg).addReg(TmpReg);
-
- // Move the low byte from the scratch space into the final destination.
- buildMI(MBB, MBBI, AVR::POPRd, DstLoReg);
- }
-
- MIBLO.setMemRefs(MI.memoperands());
- MIBHI.setMemRefs(MI.memoperands());
+ buildMI(MBB, MBBI, OpHi)
+ .addReg(DstHiReg, RegState::Define)
+ .addReg(SrcReg, getKillRegState(SrcIsKill))
+ .addImm(1)
+ .setMemRefs(MI.memoperands());
MI.eraseFromParent();
return true;
@@ -763,7 +746,6 @@ bool AVRExpandPseudo::expand<AVR::LDDWRdPtrQ>(Block &MBB, BlockIt MBBI) {
MachineInstr &MI = *MBBI;
Register DstLoReg, DstHiReg;
Register DstReg = MI.getOperand(0).getReg();
- Register TmpReg = 0; // 0 for no temporary register
Register SrcReg = MI.getOperand(1).getReg();
unsigned Imm = MI.getOperand(2).getImm();
bool SrcIsKill = MI.getOperand(1).isKill();
@@ -775,39 +757,23 @@ bool AVRExpandPseudo::expand<AVR::LDDWRdPtrQ>(Block &MBB, BlockIt MBBI) {
// highest Imm value allowed for the instruction, 62 is the limit here.
assert(Imm <= 62 && "Offset is out of range");
- // Use a temporary register if src and dst registers are the same.
- if (DstReg == SrcReg)
- TmpReg = scavengeGPR8(MI);
-
- Register CurDstLoReg = (DstReg == SrcReg) ? TmpReg : DstLoReg;
- Register CurDstHiReg = (DstReg == SrcReg) ? TmpReg : DstHiReg;
+ // DstReg has an earlyclobber so the register allocator will allocate them in
+ // separate registers.
+ assert(DstReg != SrcReg && "Dst and Src registers are the same!");
// Load low byte.
- auto MIBLO = buildMI(MBB, MBBI, OpLo)
- .addReg(CurDstLoReg, RegState::Define)
- .addReg(SrcReg)
- .addImm(Imm);
-
- // Push low byte onto stack if necessary.
- if (TmpReg)
- buildMI(MBB, MBBI, AVR::PUSHRr).addReg(TmpReg);
+ buildMI(MBB, MBBI, OpLo)
+ .addReg(DstLoReg, RegState::Define)
+ .addReg(SrcReg)
+ .addImm(Imm)
+ .setMemRefs(MI.memoperands());
// Load high byte.
- auto MIBHI = buildMI(MBB, MBBI, OpHi)
- .addReg(CurDstHiReg, RegState::Define)
- .addReg(SrcReg, getKillRegState(SrcIsKill))
- .addImm(Imm + 1);
-
- if (TmpReg) {
- // Move the high byte into the final destination.
- buildMI(MBB, MBBI, AVR::MOVRdRr, DstHiReg).addReg(TmpReg);
-
- // Move the low byte from the scratch space into the final destination.
- buildMI(MBB, MBBI, AVR::POPRd, DstLoReg);
- }
-
- MIBLO.setMemRefs(MI.memoperands());
- MIBHI.setMemRefs(MI.memoperands());
+ buildMI(MBB, MBBI, OpHi)
+ .addReg(DstHiReg, RegState::Define)
+ .addReg(SrcReg, getKillRegState(SrcIsKill))
+ .addImm(Imm + 1)
+ .setMemRefs(MI.memoperands());
MI.eraseFromParent();
return true;
diff --git a/llvm/test/CodeGen/AVR/pseudo/LDWRdPtr-same-src-dst.mir b/llvm/test/CodeGen/AVR/pseudo/LDWRdPtr-same-src-dst.mir
deleted file mode 100644
index 9ceef4c1bf850..0000000000000
--- a/llvm/test/CodeGen/AVR/pseudo/LDWRdPtr-same-src-dst.mir
+++ /dev/null
@@ -1,30 +0,0 @@
-# RUN: llc -O0 %s -o - | FileCheck %s
-
-# This test checks the expansion of the 16-bit LDWRdPtr pseudo instruction.
-
---- |
- target triple = "avr--"
- define void @test_ldwrdptr() {
- entry:
- ret void
- }
-...
-
----
-name: test_ldwrdptr
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- liveins: $r31r30
-
- ; CHECK-LABEL: test_ldwrdptr
-
- ; CHECK: ld [[SCRATCH:r[0-9]+]], Z
- ; CHECK-NEXT: push [[SCRATCH]]
- ; CHECK-NEXT: ldd [[SCRATCH]], Z+1
- ; CHECK-NEXT: mov r31, [[SCRATCH]]
- ; CHECK-NEXT: pop r30
-
- early-clobber $r31r30 = LDWRdPtr undef $r31r30
-...
-
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