[llvm] de48717 - [AVR] Support unaligned store

[Ayke van Laethem via llvm-commits]

Author: Ayke van Laethem
Date: 2022-08-15T14:29:37+02:00
New Revision: de48717fcf1c340517beb8beb488c627e6e3d034

URL: https://github.com/llvm/llvm-project/commit/de48717fcf1c340517beb8beb488c627e6e3d034
DIFF: https://github.com/llvm/llvm-project/commit/de48717fcf1c340517beb8beb488c627e6e3d034.diff

LOG: [AVR] Support unaligned store

This patch really just extends D39946 towards stores as well as loads.
While the patch is in SelectionDAGBuilder, it only applies to AVR (the
only target that supports unaligned atomic operations).

Differential Revision: https://reviews.llvm.org/D128483

Added: 
    llvm/test/CodeGen/AVR/unaligned-atomic-ops.ll

Modified: 
    llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Removed: 
    llvm/test/CodeGen/AVR/unaligned-atomic-loads.ll


################################################################################
diff  --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 5b0fa7bf3d73e..71862494112c5 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -4733,7 +4733,8 @@ void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
   EVT MemVT =
       TLI.getMemValueType(DAG.getDataLayout(), I.getValueOperand()->getType());
 
-  if (I.getAlign().value() < MemVT.getSizeInBits() / 8)
+  if (!TLI.supportsUnalignedAtomics() &&
+      I.getAlign().value() < MemVT.getSizeInBits() / 8)
     report_fatal_error("Cannot generate unaligned atomic store");
 
   auto Flags = TLI.getStoreMemOperandFlags(I, DAG.getDataLayout());

diff  --git a/llvm/test/CodeGen/AVR/unaligned-atomic-loads.ll b/llvm/test/CodeGen/AVR/unaligned-atomic-ops.ll
similarity index 78%
rename from llvm/test/CodeGen/AVR/unaligned-atomic-loads.ll
rename to llvm/test/CodeGen/AVR/unaligned-atomic-ops.ll
index db1ab33fa883c..113c851c255ab 100644
--- a/llvm/test/CodeGen/AVR/unaligned-atomic-loads.ll
+++ b/llvm/test/CodeGen/AVR/unaligned-atomic-ops.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -mattr=addsubiw < %s -march=avr | FileCheck %s
 
-; This verifies that the middle end can handle an unaligned atomic load.
+; This verifies that the backend can handle an unaligned atomic load and store.
 ;
 ; In the past, an assertion inside the SelectionDAGBuilder would always
 ; hit an assertion for unaligned loads and stores.
@@ -14,6 +14,7 @@ define void @foo(%AtomicI16* %self) {
 start:
   %a = getelementptr inbounds %AtomicI16, %AtomicI16* %self, i16 0, i32 0, i32 0
   load atomic i16, i16* %a seq_cst, align 1
+  store atomic i16 5, i16* %a seq_cst, align 1
   ret void
 }