[llvm] 40ba786 - [Hexagon] Distribute disjoint intervals at the end of expand-condsets

[Krzysztof Parzyszek via llvm-commits]

Author: Krzysztof Parzyszek
Date: 2022-08-14T16:15:23-05:00
New Revision: 40ba78679dc0376af4379b4f6c140ad1f21b6c59

URL: https://github.com/llvm/llvm-project/commit/40ba78679dc0376af4379b4f6c140ad1f21b6c59
DIFF: https://github.com/llvm/llvm-project/commit/40ba78679dc0376af4379b4f6c140ad1f21b6c59.diff

LOG: [Hexagon] Distribute disjoint intervals at the end of expand-condsets

This fixes https://github.com/llvm/llvm-project/issues/56050.

Added: 
    

Modified: 
    llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
    llvm/test/CodeGen/Hexagon/expand-condsets-def-undef.mir

Removed: 
    


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diff  --git a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
index 1a08ac6188c0..7dc154aaaea1 100644
--- a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
@@ -210,6 +210,7 @@ namespace {
     void removeInstr(MachineInstr &MI);
     void updateLiveness(const std::set<Register> &RegSet, bool Recalc,
                         bool UpdateKills, bool UpdateDeads);
+    void distributeLiveIntervals(const std::set<Register> &Regs);
 
     unsigned getCondTfrOpcode(const MachineOperand &SO, bool Cond);
     MachineInstr *genCondTfrFor(MachineOperand &SrcOp,
@@ -574,6 +575,27 @@ void HexagonExpandCondsets::updateLiveness(const std::set<Register> &RegSet,
   }
 }
 
+void HexagonExpandCondsets::distributeLiveIntervals(
+    const std::set<Register> &Regs) {
+  ConnectedVNInfoEqClasses EQC(*LIS);
+  for (Register R : Regs) {
+    if (!R.isVirtual())
+      continue;
+    LiveInterval &LI = LIS->getInterval(R);
+    unsigned NumComp = EQC.Classify(LI);
+    if (NumComp == 1)
+      continue;
+
+    SmallVector<LiveInterval*> NewLIs;
+    const TargetRegisterClass *RC = MRI->getRegClass(LI.reg());
+    for (unsigned I = 1; I < NumComp; ++I) {
+      Register NewR = MRI->createVirtualRegister(RC);
+      NewLIs.push_back(&LIS->createEmptyInterval(NewR));
+    }
+    EQC.Distribute(LI, NewLIs.begin(), *MRI);
+  }
+}
+
 /// Get the opcode for a conditional transfer of the value in SO (source
 /// operand). The condition (true/false) is given in Cond.
 unsigned HexagonExpandCondsets::getCondTfrOpcode(const MachineOperand &SO,
@@ -1320,6 +1342,9 @@ bool HexagonExpandCondsets::runOnMachineFunction(MachineFunction &MF) {
   PredUpd.insert(CoalUpd.begin(), CoalUpd.end());
   updateLiveness(PredUpd, true, true, true);
 
+  if (Changed)
+    distributeLiveIntervals(PredUpd);
+
   LLVM_DEBUG({
     if (Changed)
       LIS->print(dbgs() << "After expand-condsets\n",

diff  --git a/llvm/test/CodeGen/Hexagon/expand-condsets-def-undef.mir b/llvm/test/CodeGen/Hexagon/expand-condsets-def-undef.mir
index 531c99f1fae2..7ac04b2d5d9a 100644
--- a/llvm/test/CodeGen/Hexagon/expand-condsets-def-undef.mir
+++ b/llvm/test/CodeGen/Hexagon/expand-condsets-def-undef.mir
@@ -31,8 +31,11 @@ body: |
     %0 = COPY $p0
     %1 = COPY $r0
     %2 = COPY $d0
+    ; This copy is added by distributing disjoint live interval. Check
+    ; for it to make sure %4 is the right thing.
+    ; CHECK: %4:doubleregs = COPY $d0
     ; Check that this instruction is unchanged (remains unpredicated)
-    ; CHECK: %3:intregs = A2_addi %2.isub_hi, 1
+    ; CHECK: %3:intregs = A2_addi %4.isub_hi, 1
     %3 = A2_addi %2.isub_hi, 1
     undef %2.isub_lo = C2_mux %0, %2.isub_lo, %1
     %2.isub_hi = C2_muxir %0, %3, 0