[llvm] 98bd252 - [Hexagon] Make some loops in HexagonExpandCondsets.cpp range-based, NFC
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 14 14:16:01 PDT 2022
Author: Krzysztof Parzyszek
Date: 2022-08-14T16:15:06-05:00
New Revision: 98bd2524322e35638a7f139c643104b87e13c59f
URL: https://github.com/llvm/llvm-project/commit/98bd2524322e35638a7f139c643104b87e13c59f
DIFF: https://github.com/llvm/llvm-project/commit/98bd2524322e35638a7f139c643104b87e13c59f.diff
LOG: [Hexagon] Make some loops in HexagonExpandCondsets.cpp range-based, NFC
Plus some readability changes.
Added:
Modified:
llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
index 853553f57ba4..1a08ac6188c0 100644
--- a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
@@ -208,7 +208,7 @@ namespace {
void updateDeadFlags(Register Reg);
void recalculateLiveInterval(Register Reg);
void removeInstr(MachineInstr &MI);
- void updateLiveness(std::set<Register> &RegSet, bool Recalc,
+ void updateLiveness(const std::set<Register> &RegSet, bool Recalc,
bool UpdateKills, bool UpdateDeads);
unsigned getCondTfrOpcode(const MachineOperand &SO, bool Cond);
@@ -391,10 +391,10 @@ void HexagonExpandCondsets::updateDeadsInRange(Register Reg, LaneBitmask LM,
auto Dominate = [this] (SetVector<MachineBasicBlock*> &Defs,
MachineBasicBlock *Dest) -> bool {
- for (MachineBasicBlock *D : Defs)
+ for (MachineBasicBlock *D : Defs) {
if (D != Dest && MDT->dominates(D, Dest))
return true;
-
+ }
MachineBasicBlock *Entry = &Dest->getParent()->front();
SetVector<MachineBasicBlock*> Work(Dest->pred_begin(), Dest->pred_end());
for (unsigned i = 0; i < Work.size(); ++i) {
@@ -517,10 +517,9 @@ void HexagonExpandCondsets::updateDeadsInRange(Register Reg, LaneBitmask LM,
if (ImpUses.empty())
continue;
MachineFunction &MF = *DefI->getParent()->getParent();
- for (std::pair<RegisterRef, unsigned> P : ImpUses) {
- RegisterRef R = P.first;
+ for (auto [R, DefIdx] : ImpUses) {
MachineInstrBuilder(MF, DefI).addReg(R.Reg, RegState::Implicit, R.Sub);
- DefI->tieOperands(P.second, DefI->getNumOperands()-1);
+ DefI->tieOperands(DefIdx, DefI->getNumOperands()-1);
}
}
}
@@ -549,7 +548,7 @@ void HexagonExpandCondsets::removeInstr(MachineInstr &MI) {
MI.eraseFromParent();
}
-void HexagonExpandCondsets::updateLiveness(std::set<Register> &RegSet,
+void HexagonExpandCondsets::updateLiveness(const std::set<Register> &RegSet,
bool Recalc, bool UpdateKills,
bool UpdateDeads) {
UpdateKills |= UpdateDeads;
@@ -579,8 +578,6 @@ void HexagonExpandCondsets::updateLiveness(std::set<Register> &RegSet,
/// operand). The condition (true/false) is given in Cond.
unsigned HexagonExpandCondsets::getCondTfrOpcode(const MachineOperand &SO,
bool IfTrue) {
- using namespace Hexagon;
-
if (SO.isReg()) {
MCRegister PhysR;
RegisterRef RS = SO;
@@ -595,9 +592,9 @@ unsigned HexagonExpandCondsets::getCondTfrOpcode(const MachineOperand &SO,
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysS);
switch (TRI->getRegSizeInBits(*RC)) {
case 32:
- return IfTrue ? A2_tfrt : A2_tfrf;
+ return IfTrue ? Hexagon::A2_tfrt : Hexagon::A2_tfrf;
case 64:
- return IfTrue ? A2_tfrpt : A2_tfrpf;
+ return IfTrue ? Hexagon::A2_tfrpt : Hexagon::A2_tfrpf;
}
llvm_unreachable("Invalid register operand");
}
@@ -610,7 +607,7 @@ unsigned HexagonExpandCondsets::getCondTfrOpcode(const MachineOperand &SO,
case MachineOperand::MO_ExternalSymbol:
case MachineOperand::MO_GlobalAddress:
case MachineOperand::MO_BlockAddress:
- return IfTrue ? C2_cmoveit : C2_cmoveif;
+ return IfTrue ? Hexagon::C2_cmoveit : Hexagon::C2_cmoveif;
default:
break;
}
@@ -645,14 +642,14 @@ MachineInstr *HexagonExpandCondsets::genCondTfrFor(MachineOperand &SrcOp,
if (RegisterRef(SrcOp) == RegisterRef(DstR, DstSR))
SrcState &= ~RegState::Kill;
MIB = BuildMI(B, At, DL, HII->get(Opc))
- .addReg(DstR, DstState, DstSR)
- .addReg(PredOp.getReg(), PredState, PredOp.getSubReg())
- .addReg(SrcOp.getReg(), SrcState, SrcOp.getSubReg());
+ .addReg(DstR, DstState, DstSR)
+ .addReg(PredOp.getReg(), PredState, PredOp.getSubReg())
+ .addReg(SrcOp.getReg(), SrcState, SrcOp.getSubReg());
} else {
MIB = BuildMI(B, At, DL, HII->get(Opc))
- .addReg(DstR, DstState, DstSR)
- .addReg(PredOp.getReg(), PredState, PredOp.getSubReg())
- .add(SrcOp);
+ .addReg(DstR, DstState, DstSR)
+ .addReg(PredOp.getReg(), PredState, PredOp.getSubReg())
+ .add(SrcOp);
}
LLVM_DEBUG(dbgs() << "created an initial copy: " << *MIB);
@@ -678,9 +675,10 @@ bool HexagonExpandCondsets::split(MachineInstr &MI,
MachineBasicBlock::iterator At = MI;
auto updateRegs = [&UpdRegs] (const MachineInstr &MI) -> void {
- for (auto &Op : MI.operands())
+ for (auto &Op : MI.operands()) {
if (Op.isReg())
UpdRegs.insert(Op.getReg());
+ }
};
// If this is a mux of the same register, just replace it with COPY.
@@ -734,9 +732,10 @@ bool HexagonExpandCondsets::isPredicable(MachineInstr *MI) {
return false;
HasDef = true;
}
- for (auto &Mo : MI->memoperands())
+ for (auto &Mo : MI->memoperands()) {
if (Mo->isVolatile() || Mo->isAtomic())
return false;
+ }
return true;
}
@@ -833,14 +832,13 @@ bool HexagonExpandCondsets::canMoveMemTo(MachineInstr &TheI, MachineInstr &ToI,
bool Ordered = TheI.hasOrderedMemoryRef();
// Search for aliased memory reference in (StartI, EndI).
- for (MachineBasicBlock::iterator I = std::next(StartI); I != EndI; ++I) {
- MachineInstr *MI = &*I;
- if (MI->hasUnmodeledSideEffects())
+ for (MachineInstr &MI : llvm::make_range(std::next(StartI), EndI)) {
+ if (MI.hasUnmodeledSideEffects())
return false;
- bool L = MI->mayLoad(), S = MI->mayStore();
+ bool L = MI.mayLoad(), S = MI.mayStore();
if (!L && !S)
continue;
- if (Ordered && MI->hasOrderedMemoryRef())
+ if (Ordered && MI.hasOrderedMemoryRef())
return false;
bool Conflict = (L && IsStore) || S;
@@ -898,9 +896,10 @@ void HexagonExpandCondsets::predicateAt(const MachineOperand &DefOp,
NewI->clearKillInfo();
LIS->InsertMachineInstrInMaps(*NewI);
- for (auto &Op : NewI->operands())
+ for (auto &Op : NewI->operands()) {
if (Op.isReg())
UpdRegs.insert(Op.getReg());
+ }
}
/// In the range [First, Last], rename all references to the "old" register RO
@@ -910,16 +909,15 @@ void HexagonExpandCondsets::renameInRange(RegisterRef RO, RegisterRef RN,
unsigned PredR, bool Cond, MachineBasicBlock::iterator First,
MachineBasicBlock::iterator Last) {
MachineBasicBlock::iterator End = std::next(Last);
- for (MachineBasicBlock::iterator I = First; I != End; ++I) {
- MachineInstr *MI = &*I;
+ for (MachineInstr &MI : llvm::make_range(First, End)) {
// Do not touch instructions that are not predicated, or are predicated
// on the opposite condition.
- if (!HII->isPredicated(*MI))
+ if (!HII->isPredicated(MI))
continue;
- if (!MI->readsRegister(PredR) || (Cond != HII->isPredicatedTrue(*MI)))
+ if (!MI.readsRegister(PredR) || (Cond != HII->isPredicatedTrue(MI)))
continue;
- for (auto &Op : MI->operands()) {
+ for (auto &Op : MI.operands()) {
if (!Op.isReg() || RO != RegisterRef(Op))
continue;
Op.setReg(RN.Reg);
@@ -973,24 +971,23 @@ bool HexagonExpandCondsets::predicate(MachineInstr &TfrI, bool Cond,
// If it is, we can then ignore instructions predicated on the negated
// conditions when collecting def and use information.
bool PredValid = true;
- for (MachineBasicBlock::iterator I = std::next(DefIt); I != TfrIt; ++I) {
- if (!I->modifiesRegister(PredR, nullptr))
+ for (MachineInstr &MI : llvm::make_range(std::next(DefIt), TfrIt)) {
+ if (!MI.modifiesRegister(PredR, nullptr))
continue;
PredValid = false;
break;
}
- for (MachineBasicBlock::iterator I = std::next(DefIt); I != TfrIt; ++I) {
- MachineInstr *MI = &*I;
+ for (MachineInstr &MI : llvm::make_range(std::next(DefIt), TfrIt)) {
// If this instruction is predicated on the same register, it could
// potentially be ignored.
// By default assume that the instruction executes on the same condition
// as TfrI (Exec_Then), and also on the opposite one (Exec_Else).
unsigned Exec = Exec_Then | Exec_Else;
- if (PredValid && HII->isPredicated(*MI) && MI->readsRegister(PredR))
- Exec = (Cond == HII->isPredicatedTrue(*MI)) ? Exec_Then : Exec_Else;
+ if (PredValid && HII->isPredicated(MI) && MI.readsRegister(PredR))
+ Exec = (Cond == HII->isPredicatedTrue(MI)) ? Exec_Then : Exec_Else;
- for (auto &Op : MI->operands()) {
+ for (auto &Op : MI.operands()) {
if (!Op.isReg())
continue;
// We don't want to deal with physical registers. The reason is that
@@ -1042,9 +1039,10 @@ bool HexagonExpandCondsets::predicate(MachineInstr &TfrI, bool Cond,
bool CanDown = canMoveOver(*DefI, Defs, Uses);
// The TfrI does not access memory, but DefI could. Check if it's safe
// to move DefI down to TfrI.
- if (DefI->mayLoadOrStore())
+ if (DefI->mayLoadOrStore()) {
if (!canMoveMemTo(*DefI, TfrI, true))
CanDown = false;
+ }
LLVM_DEBUG(dbgs() << "Can move up: " << (CanUp ? "yes" : "no")
<< ", can move down: " << (CanDown ? "yes\n" : "no\n"));
@@ -1078,9 +1076,10 @@ bool HexagonExpandCondsets::predicateInBlock(MachineBasicBlock &B,
// If we didn't predicate I, we may need to remove it in case it is
// an "identity" copy, e.g. %1 = A2_tfrt %2, %1.
if (RegisterRef(MI.getOperand(0)) == RegisterRef(MI.getOperand(2))) {
- for (auto &Op : MI.operands())
+ for (auto &Op : MI.operands()) {
if (Op.isReg())
UpdRegs.insert(Op.getReg());
+ }
removeInstr(MI);
}
}
@@ -1263,10 +1262,12 @@ bool HexagonExpandCondsets::runOnMachineFunction(MachineFunction &MF) {
std::set<Register> CoalUpd, PredUpd;
SmallVector<MachineInstr*,16> Condsets;
- for (auto &B : MF)
- for (auto &I : B)
+ for (auto &B : MF) {
+ for (auto &I : B) {
if (isCondset(I))
Condsets.push_back(&I);
+ }
+ }
// Try to coalesce the target of a mux with one of its sources.
// This could eliminate a register copy in some circumstances.
@@ -1278,11 +1279,14 @@ bool HexagonExpandCondsets::runOnMachineFunction(MachineFunction &MF) {
// Updating them right before we split is the easiest, because splitting
// adds definitions which would interfere with updating kills afterwards.
std::set<Register> KillUpd;
- for (MachineInstr *MI : Condsets)
- for (MachineOperand &Op : MI->operands())
- if (Op.isReg() && Op.isUse())
+ for (MachineInstr *MI : Condsets) {
+ for (MachineOperand &Op : MI->operands()) {
+ if (Op.isReg() && Op.isUse()) {
if (!CoalUpd.count(Op.getReg()))
KillUpd.insert(Op.getReg());
+ }
+ }
+ }
updateLiveness(KillUpd, false, true, false);
LLVM_DEBUG(
LIS->print(dbgs() << "After coalescing\n", MF.getFunction().getParent()));
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