[llvm] e2d13fd - [DAG] canCreateUndefOrPoison - add freeze(shl(x, y)) -> shl(freeze(x),y) support

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2022-08-14T14:38:10+01:00
New Revision: e2d13fd096cb94f09cdb0611c9bda4cf88d3ce63

URL: https://github.com/llvm/llvm-project/commit/e2d13fd096cb94f09cdb0611c9bda4cf88d3ce63
DIFF: https://github.com/llvm/llvm-project/commit/e2d13fd096cb94f09cdb0611c9bda4cf88d3ce63.diff

LOG: [DAG] canCreateUndefOrPoison - add freeze(shl(x,y)) -> shl(freeze(x),y) support

These are guaranteed not to create undef/poison if the shift amount is known to be in range

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/test/CodeGen/X86/freeze-binary.ll

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 6b61157c16d3..a0b384ac53dd 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -4585,6 +4585,15 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts,
     return ConsiderFlags && (Op->getFlags().hasNoSignedWrap() ||
                              Op->getFlags().hasNoUnsignedWrap());
 
+  case ISD::SHL:
+    // If the max shift amount isn't in range, then the shift can create poison.
+    if (!getValidMaximumShiftAmountConstant(Op, DemandedElts))
+      return true;
+
+    // Matches hasPoisonGeneratingFlags().
+    return ConsiderFlags && (Op->getFlags().hasNoSignedWrap() ||
+                             Op->getFlags().hasNoUnsignedWrap());
+
   default:
     // Allow the target to implement this method for its nodes.
     if (Opcode >= ISD::BUILTIN_OP_END || Opcode == ISD::INTRINSIC_WO_CHAIN ||

diff  --git a/llvm/test/CodeGen/X86/freeze-binary.ll b/llvm/test/CodeGen/X86/freeze-binary.ll
index 24da88ea596e..e8ef4cc06563 100644
--- a/llvm/test/CodeGen/X86/freeze-binary.ll
+++ b/llvm/test/CodeGen/X86/freeze-binary.ll
@@ -326,15 +326,13 @@ define i32 @freeze_shl(i32 %a0) nounwind {
 ; X86-LABEL: freeze_shl:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    addl %eax, %eax
-; X86-NEXT:    shll $2, %eax
+; X86-NEXT:    shll $3, %eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: freeze_shl:
 ; X64:       # %bb.0:
 ; X64-NEXT:    # kill: def $edi killed $edi def $rdi
-; X64-NEXT:    leal (%rdi,%rdi), %eax
-; X64-NEXT:    shll $2, %eax
+; X64-NEXT:    leal (,%rdi,8), %eax
 ; X64-NEXT:    retq
   %x = shl i32 %a0, 1
   %y = freeze i32 %x
@@ -382,20 +380,14 @@ define <2 x i64> @freeze_shl_vec(<2 x i64> %a0) nounwind {
 ; X86-LABEL: freeze_shl_vec:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movdqa %xmm0, %xmm1
-; X86-NEXT:    psllq $2, %xmm1
-; X86-NEXT:    psllq $1, %xmm0
-; X86-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
-; X86-NEXT:    movapd %xmm0, %xmm1
-; X86-NEXT:    psllq $2, %xmm1
-; X86-NEXT:    psllq $1, %xmm0
+; X86-NEXT:    psllq $4, %xmm1
+; X86-NEXT:    psllq $2, %xmm0
 ; X86-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: freeze_shl_vec:
 ; X64:       # %bb.0:
-; X64-NEXT:    vmovdqa {{.*#+}} xmm1 = [2,1]
-; X64-NEXT:    vpsllvq %xmm1, %xmm0, %xmm0
-; X64-NEXT:    vpsllvq %xmm1, %xmm0, %xmm0
+; X64-NEXT:    vpsllvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
 ; X64-NEXT:    retq
   %x = shl <2 x i64> %a0, <i64 2, i64 1>
   %y = freeze <2 x i64> %x