[llvm] 9988536 - [X86] Add test coverage for add/sub/mul with freeze
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sat Aug 13 12:58:17 PDT 2022
Author: Simon Pilgrim
Date: 2022-08-13T20:57:59+01:00
New Revision: 998853689a79c7a9350424f6162a63ba50e6ac1a
URL: https://github.com/llvm/llvm-project/commit/998853689a79c7a9350424f6162a63ba50e6ac1a
DIFF: https://github.com/llvm/llvm-project/commit/998853689a79c7a9350424f6162a63ba50e6ac1a.diff
LOG: [X86] Add test coverage for add/sub/mul with freeze
Added:
llvm/test/CodeGen/X86/freeze-binary.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/freeze-binary.ll b/llvm/test/CodeGen/X86/freeze-binary.ll
new file mode 100644
index 0000000000000..613a8320c6484
--- /dev/null
+++ b/llvm/test/CodeGen/X86/freeze-binary.ll
@@ -0,0 +1,231 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-- -mattr=+sse2 | FileCheck %s --check-prefixes=X86
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2 | FileCheck %s --check-prefixes=X64
+
+define i32 @freeze_add(i32 %a0) nounwind {
+; X86-LABEL: freeze_add:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: incl %eax
+; X86-NEXT: incl %eax
+; X86-NEXT: retl
+;
+; X64-LABEL: freeze_add:
+; X64: # %bb.0:
+; X64-NEXT: # kill: def $edi killed $edi def $rdi
+; X64-NEXT: leal 1(%rdi), %eax
+; X64-NEXT: incl %eax
+; X64-NEXT: retq
+ %x = add i32 %a0, 1
+ %y = freeze i32 %x
+ %z = add i32 %y, 1
+ ret i32 %z
+}
+
+define i32 @freeze_add_nsw(i32 %a0) nounwind {
+; X86-LABEL: freeze_add_nsw:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: incl %eax
+; X86-NEXT: incl %eax
+; X86-NEXT: retl
+;
+; X64-LABEL: freeze_add_nsw:
+; X64: # %bb.0:
+; X64-NEXT: # kill: def $edi killed $edi def $rdi
+; X64-NEXT: leal 1(%rdi), %eax
+; X64-NEXT: incl %eax
+; X64-NEXT: retq
+ %x = add nsw i32 %a0, 1
+ %y = freeze i32 %x
+ %z = add i32 %y, 1
+ ret i32 %z
+}
+
+define <4 x i32> @freeze_add_vec(<4 x i32> %a0) nounwind {
+; X86-LABEL: freeze_add_vec:
+; X86: # %bb.0:
+; X86-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: retl
+;
+; X64-LABEL: freeze_add_vec:
+; X64: # %bb.0:
+; X64-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; X64-NEXT: retq
+ %x = add <4 x i32> %a0, <i32 1, i32 2, i32 3, i32 4>
+ %y = freeze <4 x i32> %x
+ %z = add <4 x i32> %y, <i32 4, i32 3, i32 2, i32 1>
+ ret <4 x i32> %z
+}
+
+define <4 x i32> @freeze_add_vec_undef(<4 x i32> %a0) nounwind {
+; X86-LABEL: freeze_add_vec_undef:
+; X86: # %bb.0:
+; X86-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: retl
+;
+; X64-LABEL: freeze_add_vec_undef:
+; X64: # %bb.0:
+; X64-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; X64-NEXT: retq
+ %x = add <4 x i32> %a0, <i32 1, i32 2, i32 3, i32 undef>
+ %y = freeze <4 x i32> %x
+ %z = add <4 x i32> %y, <i32 4, i32 3, i32 2, i32 undef>
+ ret <4 x i32> %z
+}
+
+define i32 @freeze_sub(i32 %a0) nounwind {
+; X86-LABEL: freeze_sub:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: decl %eax
+; X86-NEXT: decl %eax
+; X86-NEXT: retl
+;
+; X64-LABEL: freeze_sub:
+; X64: # %bb.0:
+; X64-NEXT: # kill: def $edi killed $edi def $rdi
+; X64-NEXT: leal -1(%rdi), %eax
+; X64-NEXT: decl %eax
+; X64-NEXT: retq
+ %x = sub i32 %a0, 1
+ %y = freeze i32 %x
+ %z = sub i32 %y, 1
+ ret i32 %z
+}
+
+define i32 @freeze_sub_nuw(i32 %a0) nounwind {
+; X86-LABEL: freeze_sub_nuw:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: decl %eax
+; X86-NEXT: decl %eax
+; X86-NEXT: retl
+;
+; X64-LABEL: freeze_sub_nuw:
+; X64: # %bb.0:
+; X64-NEXT: # kill: def $edi killed $edi def $rdi
+; X64-NEXT: leal -1(%rdi), %eax
+; X64-NEXT: decl %eax
+; X64-NEXT: retq
+ %x = sub nuw i32 %a0, 1
+ %y = freeze i32 %x
+ %z = sub i32 %y, 1
+ ret i32 %z
+}
+
+define <4 x i32> @freeze_sub_vec(<4 x i32> %a0) nounwind {
+; X86-LABEL: freeze_sub_vec:
+; X86: # %bb.0:
+; X86-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: retl
+;
+; X64-LABEL: freeze_sub_vec:
+; X64: # %bb.0:
+; X64-NEXT: vpsubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vpsubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; X64-NEXT: retq
+ %x = sub <4 x i32> %a0, <i32 1, i32 2, i32 3, i32 4>
+ %y = freeze <4 x i32> %x
+ %z = sub <4 x i32> %y, <i32 4, i32 3, i32 2, i32 1>
+ ret <4 x i32> %z
+}
+
+define <4 x i32> @freeze_sub_vec_undef(<4 x i32> %a0) nounwind {
+; X86-LABEL: freeze_sub_vec_undef:
+; X86: # %bb.0:
+; X86-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: retl
+;
+; X64-LABEL: freeze_sub_vec_undef:
+; X64: # %bb.0:
+; X64-NEXT: vpsubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vpsubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; X64-NEXT: retq
+ %x = sub <4 x i32> %a0, <i32 1, i32 2, i32 3, i32 undef>
+ %y = freeze <4 x i32> %x
+ %z = sub <4 x i32> %y, <i32 4, i32 3, i32 2, i32 undef>
+ ret <4 x i32> %z
+}
+
+define i32 @freeze_mul(i32 %a0) nounwind {
+; X86-LABEL: freeze_mul:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: addl %eax, %eax
+; X86-NEXT: addl %eax, %eax
+; X86-NEXT: retl
+;
+; X64-LABEL: freeze_mul:
+; X64: # %bb.0:
+; X64-NEXT: # kill: def $edi killed $edi def $rdi
+; X64-NEXT: leal (%rdi,%rdi), %eax
+; X64-NEXT: addl %eax, %eax
+; X64-NEXT: retq
+ %x = mul i32 %a0, 2
+ %y = freeze i32 %x
+ %z = mul i32 %y, 2
+ ret i32 %z
+}
+
+define i32 @freeze_mul_nsw(i32 %a0) nounwind {
+; X86-LABEL: freeze_mul_nsw:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: addl %eax, %eax
+; X86-NEXT: shll $2, %eax
+; X86-NEXT: retl
+;
+; X64-LABEL: freeze_mul_nsw:
+; X64: # %bb.0:
+; X64-NEXT: # kill: def $edi killed $edi def $rdi
+; X64-NEXT: leal (%rdi,%rdi), %eax
+; X64-NEXT: shll $2, %eax
+; X64-NEXT: retq
+ %x = mul nsw i32 %a0, 2
+ %y = freeze i32 %x
+ %z = mul i32 %y, 4
+ ret i32 %z
+}
+
+define <8 x i16> @freeze_mul_vec(<8 x i16> %a0) nounwind {
+; X86-LABEL: freeze_mul_vec:
+; X86: # %bb.0:
+; X86-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: retl
+;
+; X64-LABEL: freeze_mul_vec:
+; X64: # %bb.0:
+; X64-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; X64-NEXT: retq
+ %x = mul <8 x i16> %a0, <i16 1, i16 2, i16 3, i16 4, i16 4, i16 3, i16 2, i16 1>
+ %y = freeze <8 x i16> %x
+ %z = mul <8 x i16> %y, <i16 4, i16 3, i16 2, i16 1, i16 1, i16 2, i16 3, i16 4>
+ ret <8 x i16> %z
+}
+
+define <8 x i16> @freeze_mul_vec_undef(<8 x i16> %a0) nounwind {
+; X86-LABEL: freeze_mul_vec_undef:
+; X86: # %bb.0:
+; X86-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-NEXT: retl
+;
+; X64-LABEL: freeze_mul_vec_undef:
+; X64: # %bb.0:
+; X64-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; X64-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; X64-NEXT: retq
+ %x = mul <8 x i16> %a0, <i16 1, i16 2, i16 3, i16 4, i16 4, i16 3, i16 undef, i16 1>
+ %y = freeze <8 x i16> %x
+ %z = mul <8 x i16> %y, <i16 4, i16 3, i16 2, i16 1, i16 1, i16 2, i16 undef, i16 4>
+ ret <8 x i16> %z
+}
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