[PATCH] D131773: [AArch64] Add support for 256-bit non temporal loads

[Florian Hahn via Phabricator via llvm-commits]

fhahn added reviewers: ab, dmgreen, SjoerdMeijer.
fhahn added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:793
 
+  setOperationAction(ISD::LOAD, MVT::v32i8, Custom);
+  setOperationAction(ISD::LOAD, MVT::v16i16, Custom);
----------------
Could you add a comment similar to the one for the stores above?


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:800
+  setOperationAction(ISD::LOAD, MVT::v4i64, Custom);
   // Lower READCYCLECOUNTER using an mrs from PMCCNTR_EL0.
   // This requires the Performance Monitors extension.
----------------
nit: please add a newline before this comment.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:20390
+    ElementCount EC = MemVT.getVectorElementCount();
+    if (LoadNode->isNonTemporal() && MemVT.getSizeInBits() == 256u &&
+        EC.isKnownEven() &&
----------------
Would be good to have a comment here to describe what's lowered here.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:20405
+
+      // SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, SDLoc(N), MVT::i128,
+      //                            Result.getValue(0), Result.getValue(1));
----------------
leftover commented-out code?


================
Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:2588
+          (LDNPQi GPR64sp:$Rn, simm7s16:$offset)>;
 //---
 // (register offset)
----------------
nit: newline here


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131773/new/

https://reviews.llvm.org/D131773