[PATCH] D131551: [RISCV] Add binary mask pattern for vector integer binary instructions.

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan updated this revision to Diff 452147.
jacquesguan added a comment.

Use DAG combiner instead of pattern.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131551/new/

https://reviews.llvm.org/D131551

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
  llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vshl-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll

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