[PATCH] D130769: [RISCV] Combine and remove redundant ADD/SUB instructions
Elena Lepilkina via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 11 01:44:19 PDT 2022
eklepilkina marked an inline comment as done.
eklepilkina added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVAddSubCombiner.cpp:188
+ erase_if(RegistersInfo.second, [&Reg](std::pair<Register, bool> Element) {
+ [&Reg](std::pair<Register, bool> Element) {
+ return Element.first == Reg;
----------------
craig.topper wrote:
> Something looks weird here. `[&Reg](std::pair<Register, bool> Element) {` is repeated
Sorry, cherry-picked and merged badly.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D130769/new/
https://reviews.llvm.org/D130769
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