[PATCH] D131339: [RISC-V] Add explicit check for risc-v 32/64 bit triples

[Alexey Baturo via Phabricator via llvm-commits]

smd added inline comments.


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Comment at: llvm/include/llvm/ADT/Triple.h:862
 
+  /// Tests whether the target is RISC-V 32-bit.
+  bool isRISCV32() const { return getArch() == Triple::riscv32; }
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MaskRay wrote:
> The order "32-bit RISC-V" is more common.
Fixed, thanks


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131339/new/

https://reviews.llvm.org/D131339