[PATCH] D131339: [RISC-V] Add explicit check for risc-v 32/64 bit triples

[Alexey Baturo via Phabricator via llvm-commits]

smd updated this revision to Diff 451354.
smd added a comment.

Addressing comments


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D131339/new/

https://reviews.llvm.org/D131339

Files:
  llvm/include/llvm/ADT/Triple.h


Index: llvm/include/llvm/ADT/Triple.h
===================================================================
--- llvm/include/llvm/ADT/Triple.h
+++ llvm/include/llvm/ADT/Triple.h
@@ -859,10 +859,14 @@
     return getArch() == Triple::ppc64 || getArch() == Triple::ppc64le;
   }
 
+  /// Tests whether the target is 32-bit RISC-V.
+  bool isRISCV32() const { return getArch() == Triple::riscv32; }
+
+  /// Tests whether the target is 64-bit RISC-V.
+  bool isRISCV64() const { return getArch() == Triple::riscv64; }
+
   /// Tests whether the target is RISC-V (32- and 64-bit).
-  bool isRISCV() const {
-    return getArch() == Triple::riscv32 || getArch() == Triple::riscv64;
-  }
+  bool isRISCV() const { return isRISCV32() || isRISCV64(); }
 
   /// Tests whether the target is 32-bit SPARC (little and big endian).
   bool isSPARC32() const {


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