[PATCH] D131340: [RISC-V][HWASAN] Add intrinsics required for HWASAN support for RISC-V

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:1678-1679
 
+let Predicates = [IsRV64], Uses = [ X5 ],
+                           Defs = [ X1, X6, X7, X28, X29, X30, X31 ] in {
+def HWASAN_CHECK_MEMACCESS_SHORTGRANULES : Pseudo<
----------------
This formatting is not used anywhere in the RISCV backend


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Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:149
 
+def GPRNoX1X6X7X28X29X30X31 : RegisterClass<"RISCV", [XLenVT], 32, (sub GPR, X1, X6, X7, X28, X29, X30, X31)> {
+  let RegInfos = XLenRI;
----------------
smd wrote:
> craig.topper wrote:
> > I think this line probably exceeds 80 characters
> Fixed, thanks
Why is this set of registers what it is? This is not a helpful name. It looks like this is in fact the set of GPRs minus RA and all temporary registers other than t0. The AArch64 equivalent has:

```
// Register set that excludes registers that are reserved for procedure calls.
// This is used for pseudo-instructions that are actually implemented using a
// procedure call.
```


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https://reviews.llvm.org/D131340